Lines Matching defs:regs
104 volatile imx_sdhci_regs_t* regs;
153 SDHCI_ERROR(" ds_addr = 0x%x\n", readl(&dev->regs->ds_addr));
154 SDHCI_ERROR(" blk_att = 0x%x\n", readl(&dev->regs->blk_att));
155 SDHCI_ERROR(" cmd_arg = 0x%x\n", readl(&dev->regs->cmd_arg));
156 SDHCI_ERROR(" cmd_xfr_typ = 0x%x\n", readl(&dev->regs->cmd_xfr_typ));
157 SDHCI_ERROR(" cmd_rsp0 = 0x%x\n", readl(&dev->regs->cmd_rsp0));
158 SDHCI_ERROR(" cmd_rsp1 = 0x%x\n", readl(&dev->regs->cmd_rsp1));
159 SDHCI_ERROR(" cmd_rsp2 = 0x%x\n", readl(&dev->regs->cmd_rsp2));
160 SDHCI_ERROR(" cmd_rsp3 = 0x%x\n", readl(&dev->regs->cmd_rsp3));
161 SDHCI_ERROR(" data_buff_acc_port = 0x%x\n", readl(&dev->regs->data_buff_acc_port));
162 SDHCI_ERROR(" pres_state = 0x%x\n", readl(&dev->regs->pres_state));
163 SDHCI_ERROR(" prot_ctrl = 0x%x\n", readl(&dev->regs->prot_ctrl));
164 SDHCI_ERROR(" sys_ctrl = 0x%x\n", readl(&dev->regs->sys_ctrl));
165 SDHCI_ERROR(" int_status = 0x%x\n", readl(&dev->regs->int_status));
166 SDHCI_ERROR(" int_status_en = 0x%x\n", readl(&dev->regs->int_status_en));
167 SDHCI_ERROR(" int_signal_en = 0x%x\n", readl(&dev->regs->int_signal_en));
168 SDHCI_ERROR(" autocmd12_err_status = 0x%x\n", readl(&dev->regs->autocmd12_err_status));
169 SDHCI_ERROR(" host_ctrl_cap = 0x%x\n", readl(&dev->regs->host_ctrl_cap));
170 SDHCI_ERROR(" wtmk_lvl = 0x%x\n", readl(&dev->regs->wtmk_lvl));
171 SDHCI_ERROR(" mix_ctrl = 0x%x\n", readl(&dev->regs->mix_ctrl));
172 SDHCI_ERROR(" force_event = 0x%x\n", readl(&dev->regs->force_event));
173 SDHCI_ERROR(" adma_err_status = 0x%x\n", readl(&dev->regs->adma_err_status));
174 SDHCI_ERROR(" adma_sys_addr = 0x%x\n", readl(&dev->regs->adma_sys_addr));
175 SDHCI_ERROR(" dll_ctrl = 0x%x\n", readl(&dev->regs->dll_ctrl));
176 SDHCI_ERROR(" dll_status = 0x%x\n", readl(&dev->regs->dll_status));
177 SDHCI_ERROR(" clk_tune_ctrl_status = 0x%x\n", readl(&dev->regs->clk_tune_ctrl_status));
178 SDHCI_ERROR(" strobe_dll_ctrl = 0x%x\n", readl(&dev->regs->strobe_dll_ctrl));
179 SDHCI_ERROR(" strobe_dll_status = 0x%x\n", readl(&dev->regs->strobe_dll_status));
180 SDHCI_ERROR(" vend_spec = 0x%x\n", readl(&dev->regs->vend_spec));
181 SDHCI_ERROR(" mmc_boot = 0x%x\n", readl(&dev->regs->mmc_boot));
182 SDHCI_ERROR(" vend_spec2 = 0x%x\n", readl(&dev->regs->vend_spec2));
183 SDHCI_ERROR(" tuning_ctrl = 0x%x\n", readl(&dev->regs->tuning_ctrl));
282 if (!(readl(&dev->regs->sys_ctrl) & mask)) {
298 writel(0, &dev->regs->int_signal_en);
318 volatile struct imx_sdhci_regs* regs = dev->regs;
323 req->response[0] = (regs->cmd_rsp0 << 8);
324 req->response[1] = (regs->cmd_rsp1 << 8) | ((regs->cmd_rsp0 >> 24) & 0xFF);
325 req->response[2] = (regs->cmd_rsp2 << 8) | ((regs->cmd_rsp1 >> 24) & 0xFF);
326 req->response[3] = (regs->cmd_rsp3 << 8) | ((regs->cmd_rsp2 >> 24) & 0xFF);
328 req->response[0] = regs->cmd_rsp0;
329 req->response[1] = regs->cmd_rsp1;
360 *wrd = readl(&dev->regs->data_buff_acc_port); //TODO: Can't read this if DMA is enabled!
379 writel(*wrd, &dev->regs->data_buff_acc_port); //TODO: Can't write if DMA is enabled
400 set_bitsl(IMX_SDHC_SYS_CTRL_RSTC, &dev->regs->sys_ctrl);
402 set_bitsl( IMX_SDHC_SYS_CTRL_RSTD, &dev->regs->sys_ctrl);
460 volatile struct imx_sdhci_regs* regs = dev->regs;
463 regs->int_signal_en = normal_interrupts | error_interrupts;
470 const uint32_t irq = regs->int_status;
471 SDHCI_TRACE("got irq 0x%08x[stat 0x%08x en 0x%08x sig 0x%08x\n",irq, regs->int_status,
472 regs->int_status_en, regs->int_signal_en);
477 regs->int_signal_en = 0; // disable for now
480 regs->int_status = irq;
489 regs->adma_err_status, regs->adma_sys_addr);
600 volatile struct imx_sdhci_regs* regs = dev->regs;
626 while(readl(®s->pres_state) & inhibit_mask) {
641 writel((uint32_t)desc_phys, ®s->adma_sys_addr);
642 clr_bitsl(IMX_SDHC_PROT_CTRL_DMASEL_MASK, &dev->regs->prot_ctrl);
643 set_bitsl(IMX_SDHC_PROT_CTRL_DMASEL_ADMA2, &dev->regs->prot_ctrl);
644 writel(0, ®s->adma_err_status);
645 set_bitsl(IMX_SDHC_MIX_CTRL_DMAEN, ®s->mix_ctrl);
647 clr_bitsl(IMX_SDHC_PROT_CTRL_DMASEL_MASK, &dev->regs->prot_ctrl);
654 writel(blksiz | (blkcnt << 16), ®s->blk_att);
655 writel((blksiz/4) | (blksiz/4) << 16, &dev->regs->wtmk_lvl);
657 writel(arg, ®s->cmd_arg);
660 writel(0xFFFFFFFF, ®s->int_status);
664 writel(error_interrupts | dma_normal_interrupts, ®s->int_signal_en);
665 writel(error_interrupts | dma_normal_interrupts, ®s->int_status_en);
668 writel(error_interrupts | normal_interrupts, ®s->int_signal_en);
669 writel(error_interrupts | normal_interrupts, ®s->int_status_en);
683 clr_bitsl(IMX_SDHC_MIX_CTRL_CMD_MASK, ®s->mix_ctrl);
684 set_bitsl(cmd & IMX_SDHC_MIX_CTRL_CMD_MASK, ®s->mix_ctrl);
685 writel(cmd & IMX_SDHC_CMD_XFER_TYPE_CMD_MASK, ®s->cmd_xfr_typ);
692 while((readl(®s->int_status) & readl(®s->int_status_en)) == 0) {
697 const uint32_t irq = readl(®s->int_status);
699 readl(®s->int_status), irq, readl(®s->int_status_en), readl(®s->int_signal_en),
703 writel(irq, ®s->int_status);
711 readl(®s->adma_err_status), readl(®s->adma_sys_addr));
800 clr_bitsl(IMX_SDHC_PROT_CTRL_DTW_MASK, &dev->regs->prot_ctrl);
801 set_bitsl(IMX_SDHC_PROT_CTRL_DTW_1, &dev->regs->prot_ctrl);
804 clr_bitsl(IMX_SDHC_PROT_CTRL_DTW_MASK, &dev->regs->prot_ctrl);
805 set_bitsl(IMX_SDHC_PROT_CTRL_DTW_4, &dev->regs->prot_ctrl);
808 clr_bitsl(IMX_SDHC_PROT_CTRL_DTW_MASK, &dev->regs->prot_ctrl);
809 set_bitsl(IMX_SDHC_PROT_CTRL_DTW_8, &dev->regs->prot_ctrl);
837 volatile struct imx_sdhci_regs* regs = dev->regs;
840 while (readl(®s->pres_state) & (IMX_SDHC_PRES_STATE_CIHB | IMX_SDHC_PRES_STATE_CDIHB)) {
849 set_bitsl(IMX_SDHC_MIX_CTRL_DDR_EN, ®s->mix_ctrl);
852 clr_bitsl(IMX_SDHC_VEND_SPEC_CARD_CLK_SOFT_EN, ®s->vend_spec);
854 clr_bitsl(IMX_SDHC_SYS_CTRL_CLOCK_MASK, ®s->sys_ctrl);
858 ®s->sys_ctrl);
864 ®s->vend_spec);
879 clr_bitsl(IMX_SDHC_VEND_SPEC_FRC_SDCLK_ON, &dev->regs->vend_spec);
880 writel(IMX_SDHC_DLLCTRL_RESET, &dev->regs->dll_ctrl);
882 writel((IMX_SDHC_DLLCTRL_ENABLE | IMX_SDHC_DLLCTRL_SLV_DLY_TARGET), &dev->regs->dll_ctrl);
884 if(!(readl(&dev->regs->dll_status) & IMX_SDHC_DLLSTS_REF_LOCK)) {
887 if(!(readl(&dev->regs->dll_status) & IMX_SDHC_DLLSTS_SLV_LOCK)) {
905 uint32_t regVal = readl(&dev->regs->mix_ctrl);
914 &dev->regs->autocmd12_err_status);
918 writel(regVal, &dev->regs->mix_ctrl);
934 writel(regVal, &dev->regs->mix_ctrl);
957 set_bitsl(IMX_SDHC_SYS_CTRL_RSTA, &dev->regs->sys_ctrl);
959 SDHCI_ERROR("Did not recover from reset 0x%x\n", readl(&dev->regs->sys_ctrl));
964 writel(0, &dev->regs->mmc_boot);
965 writel(0, &dev->regs->mix_ctrl);
966 writel(0, &dev->regs->clk_tune_ctrl_status);
967 writel(0, &dev->regs->dll_ctrl);
968 writel(0, &dev->regs->autocmd12_err_status);
969 writel(IMX_SDHC_VEND_SPEC_INIT, &dev->regs->vend_spec);
971 &dev->regs->vend_spec);
972 clr_bitsl(IMX_SDHC_SYS_CTRL_DTOCV_MASK, &dev->regs->sys_ctrl);
973 set_bitsl(IMX_SDHC_SYS_CTRL_DTOCV(0xe), &dev->regs->sys_ctrl);
974 writel(IMX_SDHC_PROT_CTRL_INIT, &dev->regs->prot_ctrl);
976 uint32_t regVal = readl(&dev->regs->tuning_ctrl);
983 writel(regVal, &dev->regs->tuning_ctrl);
985 set_bitsl(1 << 1, &dev->regs->vend_spec);
1042 .blocksize = (readl(&dev->regs->prot_ctrl) & IMX_SDHC_PROT_CTRL_DTW_8) ? 128 : 64,
1046 regVal = readl(&dev->regs->autocmd12_err_status);
1049 writel(regVal, &dev->regs->autocmd12_err_status);
1051 regVal = readl(&dev->regs->mix_ctrl);
1054 writel(regVal, &dev->regs->mix_ctrl);
1066 } while (((readl(&dev->regs->autocmd12_err_status) & IMX_SDHC_AUTOCMD12_ERRSTS_EXE_TUNING)) &&
1069 bool fail = (readl(&dev->regs->autocmd12_err_status) & IMX_SDHC_AUTOCMD12_ERRSTS_EXE_TUNING) ||
1070 !(readl(&dev->regs->autocmd12_err_status) & IMX_SDHC_AUTOCMD12_ERRSTS_SMP_CLK_SEL);
1141 dev->regs = dev->mmios.vaddr;
1172 uint32_t caps0 = readl(&dev->regs->host_ctrl_cap);
1199 clr_bitsl(IMX_SDHC_PROT_CTRL_DMASEL_MASK, &dev->regs->prot_ctrl);
1200 set_bitsl(IMX_SDHC_PROT_CTRL_DMASEL_ADMA2, &dev->regs->prot_ctrl);
1212 writel(0, &dev->regs->int_signal_en);
1213 writel(0xffffffff, & dev->regs->int_status);