Lines Matching defs:clk_div
364 uint32_t clk_val, clk_div;
366 clk_div = get_bits(clk_val, AML_SD_EMMC_CLOCK_CFG_DIV_MASK, AML_SD_EMMC_CLOCK_CFG_DIV_LOC);
371 clk_div, &best_win_start, &best_win_size,
378 clk_div = get_bits(clk_val, AML_SD_EMMC_CLOCK_CFG_DIV_MASK,
380 clk_div += 2;
381 if (clk_div > (AML_SD_EMMC_CLOCK_CFG_DIV_MASK >> AML_SD_EMMC_CLOCK_CFG_DIV_LOC)) {
382 clk_div = AML_SD_EMMC_CLOCK_CFG_DIV_MASK >> AML_SD_EMMC_CLOCK_CFG_DIV_LOC;
385 clk_div);
389 uint32_t cur_freq = (get_clk_freq(clk_src)) / clk_div;
408 clk_div = get_bits(clk_val, AML_SD_EMMC_CLOCK_CFG_DIV_MASK, AML_SD_EMMC_CLOCK_CFG_DIV_LOC);
409 if (best_win_size != clk_div) {
411 best_adj_delay = best_adj_delay % clk_div;
429 uint32_t clk = 0, clk_src = 0, clk_div = 0;
446 clk_div = clk / freq;
447 update_bits(&clk_val, AML_SD_EMMC_CLOCK_CFG_DIV_MASK, AML_SD_EMMC_CLOCK_CFG_DIV_LOC, clk_div);
509 uint32_t clk_div = get_bits(clk_val, AML_SD_EMMC_CLOCK_CFG_DIV_MASK,
511 if (clk_div & 0x01) {
512 clk_div++;
514 clk_div /= 2;
516 clk_div);