block/ahci/ahci.c

131     uint32_t cmd = ahci_read(&port->regs->cmd);
132     if (!(cmd & AHCI_PORT_CMD_ST)) return;
133     cmd &= ~AHCI_PORT_CMD_ST;
134     ahci_write(&port->regs->cmd, cmd);
135     zx_status_t status = ahci_wait_for_clear(&port->regs->cmd, AHCI_PORT_CMD_CR, 500 * 1000 * 1000);
142     uint32_t cmd = ahci_read(&port->regs->cmd);
143     if (cmd & AHCI_PORT_CMD_ST) return;
144     if (!(cmd & AHCI_PORT_CMD_FRE)) {
148     zx_status_t status = ahci_wait_for_clear(&port->regs->cmd, AHCI_PORT_CMD_CR, 500 * 1000 * 1000);
152     cmd |= AHCI_PORT_CMD_ST;
153     ahci_write(&port->regs->cmd, cmd);
197 static bool cmd_is_read(uint8_t cmd) {
198     if (cmd == SATA_CMD_READ_DMA ||
199         cmd == SATA_CMD_READ_DMA_EXT ||
200         cmd == SATA_CMD_READ_FPDMA_QUEUED) {
207 static bool cmd_is_write(uint8_t cmd) {
208     if (cmd == SATA_CMD_WRITE_DMA ||
209         cmd == SATA_CMD_WRITE_DMA_EXT ||
210         cmd == SATA_CMD_WRITE_FPDMA_QUEUED) {
217 static bool cmd_is_queued(uint8_t cmd) {
218     return (cmd == SATA_CMD_READ_FPDMA_QUEUED) || (cmd == SATA_CMD_WRITE_FPDMA_QUEUED);
249     bool is_write = cmd_is_write(txn->cmd);
269     uint8_t cmd = txn->cmd;
276         if (cmd == SATA_CMD_READ_DMA_EXT) {
277             cmd = SATA_CMD_READ_FPDMA_QUEUED;
278         } else if (cmd == SATA_CMD_WRITE_DMA_EXT) {
279             cmd = SATA_CMD_WRITE_FPDMA_QUEUED;
295     cfis[2] = cmd;
299     if (cmd == SATA_CMD_READ_DMA_EXT ||
300         cmd == SATA_CMD_WRITE_DMA_EXT) {
309     } else if (cmd_is_queued(cmd)) {
362     if (cmd_is_queued(cmd)) {
375     uint32_t cmd = ahci_read(&port->regs->cmd);
376     if (cmd & (AHCI_PORT_CMD_ST | AHCI_PORT_CMD_FRE | AHCI_PORT_CMD_CR | AHCI_PORT_CMD_FR)) {
431     cmd |= AHCI_PORT_CMD_SUD;
432     ahci_write(&port->regs->cmd, cmd);
435     cmd &= ~AHCI_PORT_CMD_ICC_MASK;
436     cmd |= AHCI_PORT_CMD_ICC_ACTIVE;
437     ahci_write(&port->regs->cmd, cmd);
440     cmd |= AHCI_PORT_CMD_FRE;
441     ahci_write(&port->regs->cmd, cmd);
489     // put the cmd on the queue