block/ahci/ahci.c

55     ahci_port_reg_t* regs;
74     ahci_hba_t* regs;
131     uint32_t cmd = ahci_read(&port->regs->cmd);
134     ahci_write(&port->regs->cmd, cmd);
135     zx_status_t status = ahci_wait_for_clear(&port->regs->cmd, AHCI_PORT_CMD_CR, 500 * 1000 * 1000);
142     uint32_t cmd = ahci_read(&port->regs->cmd);
148     zx_status_t status = ahci_wait_for_clear(&port->regs->cmd, AHCI_PORT_CMD_CR, 500 * 1000 * 1000);
153     ahci_write(&port->regs->cmd, cmd);
161     ahci_write(&port->regs->serr, ahci_read(&port->regs->serr));
164     zx_status_t status = ahci_wait_for_clear(&port->regs->tfd, AHCI_PORT_TFD_BUSY | AHCI_PORT_TFD_DATA_REQUEST, 1000 * 1000 * 1000);
170         ahci_write(&port->regs->sctl, sctl);
172         sctl = ahci_read(&port->regs->sctl);
174         ahci_write(&port->regs->sctl, sctl);
181     status = ahci_wait_for_set(&port->regs->ssts, AHCI_PORT_SSTS_DET_PRESENT, 1llu * 1000 * 1000 * 1000);
187     ahci_write(&port->regs->serr, ahci_read(&port->regs->serr));
192     return ((ahci_read(&port->regs->sact) | ahci_read(&port->regs->ci)) & (1 << slot)) ||
223     uint32_t sact = ahci_read(&port->regs->sact);
363         ahci_write(&port->regs->sact, (1 << slot));
365     ahci_write(&port->regs->ci, (1 << slot));
375     uint32_t cmd = ahci_read(&port->regs->cmd);
402     ahci_write(&port->regs->clb, LO32(mem_phys));
403     ahci_write(&port->regs->clbu, HI32(mem_phys));
409     ahci_write(&port->regs->fb, LO32(mem_phys));
410     ahci_write(&port->regs->fbu, HI32(mem_phys));
425     ahci_write(&port->regs->is, ahci_read(&port->regs->is));
428     ahci_write(&port->regs->serr, ahci_read(&port->regs->serr));
432     ahci_write(&port->regs->cmd, cmd);
437     ahci_write(&port->regs->cmd, cmd);
441     ahci_write(&port->regs->cmd, cmd);
447     uint32_t ghc = ahci_read(&dev->regs->ghc);
451         ahci_write(&dev->regs->ghc, ghc);
452         ghc = ahci_read(&dev->regs->ghc);
460     uint32_t ghc = ahci_read(&dev->regs->ghc);
462     ahci_write(&dev->regs->ghc, ghc);
464     ahci_write(&dev->regs->ghc, ghc);
466     zx_status_t status = ahci_wait_for_clear(&dev->regs->ghc, AHCI_GHC_HR, 1000 * 1000 * 1000);
657     uint32_t is = ahci_read(&port->regs->is);
658     ahci_write(&port->regs->is, is);
661         uint32_t serr = ahci_read(&port->regs->serr);
662         ahci_write(&port->regs->serr, serr & ~0x1);
682         uint32_t ghc = ahci_read(&dev->regs->ghc);
683         ahci_write(&dev->regs->ghc, ghc & ~AHCI_GHC_IE);
686         uint32_t is = ahci_read(&dev->regs->is);
687         ahci_write(&dev->regs->is, is);
696         ghc = ahci_read(&dev->regs->ghc);
697         ahci_write(&dev->regs->ghc, ghc | AHCI_GHC_IE);
720     dev->cap = ahci_read(&dev->regs->cap);
723     uint32_t port_map = ahci_read(&dev->regs->pi);
735         port->regs = &dev->regs->ports[i];
743     ahci_write(&dev->regs->is, ahci_read(&dev->regs->is));
746     uint32_t ghc = ahci_read(&dev->regs->ghc);
748     ahci_write(&dev->regs->ghc, ghc);
759         ahci_write(&port->regs->ie, AHCI_PORT_INT_MASK);
765         if (ahci_read(&port->regs->ssts) & AHCI_PORT_SSTS_DET_PRESENT) {
767             if (ahci_read(&port->regs->sig) == AHCI_PORT_SIG_SATA) {
798                                           (void**)&device->regs,