Lines Matching refs:val
46 spr_tcp_state(val("t_state")),
47 val("t_state"),
48 spr_ip_version(val("ip_version")),
49 val("lock_tid"),
50 val("rss_fw")
53 val("l2t_ix"),
54 val("smac_sel"),
55 val("tos")
58 val("t_maxseg"), val("recv_scale"),
59 val("recv_tstmp"), val("recv_sack"));
64 val("timer"), val("dack_timer"));
66 val("mod_schd_tx"),
67 val("mod_schd_rx"),
68 ((val("mod_schd_reason2")<<2) | (val("mod_schd_reason1")<<1) |
69 val("mod_schd_reason0"))
74 val("max_rt"), val("t_rxtshift"),
75 val("keepalive"));
77 val("timestamp_offset"),val("timestamp"));
81 val("t_rtt_ts_recent_age"), val("t_rtseq_recent"));
83 val("t_srtt"),val("t_rttvar"));
92 val("snd_una"),val("snd_nxt"),
93 val("snd_max"),val("tx_max"));
95 val("core_fin"), SEQ_SUB(val("tx_max"),val("snd_una"))
97 if (val("recv_scale") && !val("active_open")) {
99 val("rcv_adv"), val("rcv_scale"),
100 val("rcv_adv") << val("rcv_scale"),
101 val("recv_scale"), val("rcv_scale"), val("active_open"));
104 val("rcv_adv"), val("rcv_scale"),
105 val("recv_scale"), val("active_open"));
109 val("snd_cwnd") , val("snd_ssthresh"), val("snd_rec")
116 spr_cctrl_sel(val("cctrl_sel0"),val("cctrl_sel1")),
117 val("cctrl_ecn"), val("cctrl_ece"), val("cctrl_cwr"),
118 val("cctrl_rfr"));
120 val("t_dupacks"), val("dupack_count_odd"),val("fast_recovery"));
122 val("core_more"),val("core_urg"),val("core_push"));
123 PR(" core_flush %u\n",val("core_flush"));
125 val("nagle"), val("ssws_disabled"), val("turbo"));
126 PR(" tx_pdu_out %u\n",val("tx_pdu_out"));
128 val("tx_pace_auto"),val("tx_pace_fixed"),val("tx_queue"));
131 PR(" tx_quiesce %u\n",val("tx_quiesce"));
133 val("tx_channel"),
134 (val("tx_channel")>>1)&1,
135 val("tx_channel")&1
142 val("tx_hdr_ptr"),val("tx_last_ptr"),val("tx_compact"));
149 val("ts_last_ack_sent"),val("rx_compact"));
151 val("rcv_nxt"), val("rx_hdr_offset"));
153 val("rx_frag0_start_idx"),
154 val("rx_frag0_len"),
155 val("rx_ptr"));
157 val("rx_frag1_start_idx_offset"),
158 val("rx_frag1_len"));
163 if (val("ulp_type")!=4) { /* RDMA has FRAG1 idx && len, but no ptr? Should I not display frag1 at all? */
164 PR("frag1_ptr 0x%-8x\n",val("rx_frag1_ptr"));
170 if (val("ulp_type") != 9 && val("ulp_type")!=8 && val("ulp_type") !=6 &&
171 val("ulp_type") != 5 && val("ulp_type") !=4) {
173 val("rx_frag2_start_idx_offset"),
174 val("rx_frag2_len"),
175 val("rx_frag2_ptr"));
177 val("rx_frag3_start_idx_offset"),
178 val("rx_frag3_len"),
179 val("rx_frag3_ptr"));
188 val("peer_fin"),val("rx_pdu_out"), val("pdu_len"));
193 if (val("recv_scale")) {
195 val("rcv_wnd"), val("snd_scale"),
196 val("rcv_wnd") >> val("snd_scale"),
197 val("recv_scale"));
200 val("rcv_wnd"), val("snd_scale"),
201 val("recv_scale"));
208 val("dack_mss"),val("dack"),val("dack_not_acked"));
210 val("rcv_coalesce_enable"),
211 val("rcv_coalesce_push"),
212 val("rcv_coalesce_last_psh"),
213 val("rcv_coalesce_heartbeat"));
216 val("rx_channel"), val("rx_quiesce"),
217 val("rx_flow_control_disable"));
219 val("rx_flow_control_ddp"));
224 ((val("pend_ctl2")<<2) | (val("pend_ctl1")<<1) |
225 val("pend_ctl0")),
226 val("core_bypass"),val("main_slush"));
228 val("migrating"),
229 val("ask_mode"), val("non_offload"), val("rss_info"));
231 val("ulp_type"), spr_ulp_type(val("ulp_type")),
232 val("ulp_raw"));
236 PR(", ulp_ext %u",val("ulp_ext"));
244 val("rdma_error"), val("rdma_flm_error"));
254 val("aux1_slush0"), val("aux1_slush1"));
255 PR(" pdu_hdr_len %u\n",val("pdu_hdr_len"));
267 val("qp_id"), val("pd_id"),val("stag"));
269 val("irs_ulp"),val("iss_ulp"));
271 val("tx_pdu_len"));
273 val("cq_idx_sq"),val("cq_idx_rq"));
275 val("rq_start"),val("rq_msn"),val("rq_max_offset"),
276 val("rq_write_ptr"));
278 val("ord_l_bit_vld"),val("rdmap_opcode"));
280 val("tx_flush"),val("tx_oos_rxmt"),val("tx_oos_txmt"));
295 val("aux3_slush"),val("ddp_buf0_unused"),val("ddp_buf1_unused"));
299 val("ddp_indicate_fll"),val("tls_key_mode"));
304 val("ddp_off"),val("ddp_active_buf"),val("ddp_indicate_out"),
305 val("ddp_wait_frag"),val("ddp_rx2tx"),val("ddp_buf_inf")
311 val("ddp_buf0_indicate"),
312 val("ddp_pshf_enable_0"), val("ddp_push_disable_0"),
313 val("ddp_buf0_flush"), val("ddp_psh_no_invalidate0")
316 val("ddp_buf1_indicate"),
317 val("ddp_pshf_enable_1"), val("ddp_push_disable_1"),
318 val("ddp_buf1_flush"), val("ddp_psh_no_invalidate1")
332 val("ddp_buf0_valid"),val("rx_ddp_buf0_offset"),
333 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_tag")
337 if (0==val("ddp_off") && 1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) {
345 val("ddp_buf1_valid"),val("rx_ddp_buf1_offset"),
346 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_tag")
352 if (0==val("ddp_off") && 1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
363 if (1==val("ddp_off")) {
365 } else if (1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) {
368 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"),
369 val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset")
371 if (1==val("ddp_buf1_valid")) {
373 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"),
374 val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset")
377 } else if (1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
380 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"),
381 val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset")
383 if (1==val("ddp_buf0_valid")) {
385 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"),
386 val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset")
389 } else if (0==val("ddp_buf0_valid") && 1==val("ddp_buf1_valid") && 0==val("ddp_active_buf")) {
391 } else if (1==val("ddp_buf0_valid") && 0==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
399 if (0==val("ddp_indicate_out")) {
400 if (0==val("ddp_buf0_indicate") && 0==val("ddp_buf1_indicate")) {
402 if (0==val("rx_hdr_offset")) {
406 val("rx_hdr_offset"));
411 } else if (1==val("ddp_indicate_out")) {
413 if (0==val("rx_hdr_offset")) {
417 val("rx_hdr_offset"));
432 val("rx_tls_buf_offset"),val("rx_tls_buf_len"),
433 val("rx_tls_flags"));
436 val("rx_tls_buf_tag"),val("rx_tls_key_tag"));