usr.sbin/bhyve/uart_emul.c

145 uart_intr_reason(struct uart_ns16550_softc *sc)
148 	if ((sc->lsr & LSR_OE) != 0 && (sc->ier & IER_ERLS) != 0)
150 	else if (uart_rxfifo_numchars(sc->backend) > 0 &&
151 	    (sc->ier & IER_ERXRDY) != 0)
153 	else if (sc->thre_int_pending && (sc->ier & IER_ETXRDY) != 0)
155 	else if ((sc->msr & MSR_DELTA_MASK) != 0 && (sc->ier & IER_EMSC) != 0)
162 uart_reset(struct uart_ns16550_softc *sc)
167 	sc->dll = divisor;
168 	sc->dlh = divisor >> 16;
169 	sc->msr = modem_status(sc->mcr);
171 	uart_rxfifo_reset(sc->backend, 1);
179 uart_toggle_intr(struct uart_ns16550_softc *sc)
183 	intr_reason = uart_intr_reason(sc);
186 		(*sc->intr_deassert)(sc->arg);
188 		(*sc->intr_assert)(sc->arg);
194 	struct uart_ns16550_softc *sc;
197 	sc = arg;
206 	uart_softc_lock(sc->backend);
208 	loopback = (sc->mcr & MCR_LOOPBACK) != 0;
209 	uart_rxfifo_drain(sc->backend, loopback);
211 		uart_toggle_intr(sc);
213 	uart_softc_unlock(sc->backend);
217 uart_ns16550_write(struct uart_ns16550_softc *sc, int offset, uint8_t value)
222 	uart_softc_lock(sc->backend);
227 	if ((sc->lcr & LCR_DLAB) != 0) {
229 			sc->dll = value;
234 			sc->dlh = value;
241 		if (uart_rxfifo_putchar(sc->backend, value,
242 		    (sc->mcr & MCR_LOOPBACK) != 0))
243 			sc->lsr |= LSR_OE;
244 		sc->thre_int_pending = true;
248 		if ((sc->ier & IER_ETXRDY) == 0 && (value & IER_ETXRDY) != 0)
249 			sc->thre_int_pending = true;
254 		sc->ier = value & 0x0F;
261 		if ((sc->fcr & FCR_ENABLE) ^ (value & FCR_ENABLE)) {
263 			    uart_rxfifo_size(sc->backend) : 1;
264 			uart_rxfifo_reset(sc->backend, fifosz);
272 			sc->fcr = 0;
275 				uart_rxfifo_reset(sc->backend,
276 				    uart_rxfifo_size(sc->backend));
278 			sc->fcr = value &
283 		sc->lcr = value;
287 		sc->mcr = value & 0x1F;
288 		msr = modem_status(sc->mcr);
295 		if ((msr & MSR_CTS) ^ (sc->msr & MSR_CTS))
296 			sc->msr |= MSR_DCTS;
297 		if ((msr & MSR_DSR) ^ (sc->msr & MSR_DSR))
298 			sc->msr |= MSR_DDSR;
299 		if ((msr & MSR_DCD) ^ (sc->msr & MSR_DCD))
300 			sc->msr |= MSR_DDCD;
301 		if ((sc->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0)
302 			sc->msr |= MSR_TERI;
308 		sc->msr &= MSR_DELTA_MASK;
309 		sc->msr |= msr;
323 		sc->scr = value;
330 	uart_toggle_intr(sc);
331 	uart_softc_unlock(sc->backend);
335 uart_ns16550_read(struct uart_ns16550_softc *sc, int offset)
339 	uart_softc_lock(sc->backend);
344 	if ((sc->lcr & LCR_DLAB) != 0) {
346 			reg = sc->dll;
351 			reg = sc->dlh;
358 		reg = uart_rxfifo_getchar(sc->backend);
361 		reg = sc->ier;
364 		iir = (sc->fcr & FCR_ENABLE) ? IIR_FIFO_MASK : 0;
366 		intr_reason = uart_intr_reason(sc);
372 			sc->thre_int_pending = false;
379 		reg = sc->lcr;
382 		reg = sc->mcr;
386 		sc->lsr |= LSR_TEMT | LSR_THRE;
389 		if (uart_rxfifo_numchars(sc->backend) > 0)
390 			sc->lsr |= LSR_RXRDY;
392 			sc->lsr &= ~LSR_RXRDY;
394 		reg = sc->lsr;
397 		sc->lsr &= ~LSR_OE;
403 		reg = sc->msr;
404 		sc->msr &= ~MSR_DELTA_MASK;
407 		reg = sc->scr;
415 	uart_toggle_intr(sc);
416 	uart_softc_unlock(sc->backend);
439 	struct uart_ns16550_softc *sc;
441 	sc = calloc(1, sizeof(struct uart_ns16550_softc));
443 	sc->arg = arg;
444 	sc->intr_assert = intr_assert;
445 	sc->intr_deassert = intr_deassert;
446 	sc->backend = uart_init();
448 	uart_reset(sc);
450 	return (sc);
454 uart_ns16550_tty_open(struct uart_ns16550_softc *sc, const char *device)
456 	return (uart_tty_open(sc->backend, device, uart_drain, sc));
461 uart_ns16550_snapshot(struct uart_ns16550_softc *sc,
466 	SNAPSHOT_VAR_OR_LEAVE(sc->data, meta, ret, done);
467 	SNAPSHOT_VAR_OR_LEAVE(sc->ier, meta, ret, done);
468 	SNAPSHOT_VAR_OR_LEAVE(sc->lcr, meta, ret, done);
469 	SNAPSHOT_VAR_OR_LEAVE(sc->mcr, meta, ret, done);
470 	SNAPSHOT_VAR_OR_LEAVE(sc->lsr, meta, ret, done);
471 	SNAPSHOT_VAR_OR_LEAVE(sc->msr, meta, ret, done);
472 	SNAPSHOT_VAR_OR_LEAVE(sc->fcr, meta, ret, done);
473 	SNAPSHOT_VAR_OR_LEAVE(sc->scr, meta, ret, done);
475 	SNAPSHOT_VAR_OR_LEAVE(sc->dll, meta, ret, done);
476 	SNAPSHOT_VAR_OR_LEAVE(sc->dlh, meta, ret, done);
478 	ret = uart_rxfifo_snapshot(sc->backend, meta);
480 	sc->thre_int_pending = 1;