Lines Matching refs:mac
162 static inline bool bwn_nphy_ipa(struct bwn_mac *mac)
164 bwn_band_t band = bwn_current_band(mac);
165 return ((mac->mac_phy.phy_n->ipa2g_on && band == BWN_BAND_2G) ||
166 (mac->mac_phy.phy_n->ipa5g_on && band == BWN_BAND_5G));
170 static uint8_t bwn_nphy_get_rx_core_state(struct bwn_mac *mac)
172 return (BWN_PHY_READ(mac, BWN_NPHY_RFSEQCA) & BWN_NPHY_RFSEQCA_RXEN) >>
181 static void bwn_nphy_force_rf_sequence(struct bwn_mac *mac,
193 uint16_t seq_mode = BWN_PHY_READ(mac, BWN_NPHY_RFSEQMODE);
196 BWN_WARNPRINTF(mac->mac_sc, "%s: seq %d > max", __func__, seq);
199 BWN_PHY_SET(mac, BWN_NPHY_RFSEQMODE,
201 BWN_PHY_SET(mac, BWN_NPHY_RFSEQTR, trigger[seq]);
203 if (!(BWN_PHY_READ(mac, BWN_NPHY_RFSEQST) & trigger[seq]))
207 BWN_ERRPRINTF(mac->mac_sc, "RF sequence status timeout\n");
209 BWN_PHY_WRITE(mac, BWN_NPHY_RFSEQMODE, seq_mode);
212 static void bwn_nphy_rf_ctl_override_rev19(struct bwn_mac *mac, uint16_t field,
220 static void bwn_nphy_rf_ctl_override_rev7(struct bwn_mac *mac, uint16_t field,
224 struct bwn_phy *phy = &mac->mac_phy;
235 BWN_WARNPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n",
242 e = bwn_nphy_get_rf_ctl_over_rev7(mac, field, override);
246 BWN_ERRPRINTF(mac->mac_sc, "Invalid override value %d\n", override);
255 BWN_PHY_MASK(mac, en_addr, ~en_mask);
257 BWN_PHY_MASK(mac, val_addr, ~e->val_mask);
260 BWN_PHY_SET(mac, en_addr, en_mask);
262 BWN_PHY_SETMASK(mac, val_addr, ~e->val_mask, (value << e->val_shift));
269 static void bwn_nphy_rf_ctl_override_one_to_many(struct bwn_mac *mac,
273 struct bwn_phy *phy = &mac->mac_phy;
277 BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n",
284 bwn_nphy_rf_ctl_override_rev7(mac, 0x20, value, core, off, 1);
285 bwn_nphy_rf_ctl_override_rev7(mac, 0x10, value, core, off, 1);
286 bwn_nphy_rf_ctl_override_rev7(mac, 0x08, value, core, off, 1);
289 bwn_nphy_rf_ctl_override_rev7(mac, 0x4, value, core, off, 1);
290 bwn_nphy_rf_ctl_override_rev7(mac, 0x2, value, core, off, 1);
291 bwn_nphy_rf_ctl_override_rev7(mac, 0x1, value, core, off, 1);
292 bwn_nphy_rf_ctl_override_rev7(mac, 0x2, value, core, off, 2);
293 bwn_nphy_rf_ctl_override_rev7(mac, 0x0800, 0, core, off, 1);
296 bwn_nphy_rf_ctl_override_rev7(mac, 0x4, value, core, off, 0);
297 bwn_nphy_rf_ctl_override_rev7(mac, 0x2, value, core, off, 1);
298 bwn_nphy_rf_ctl_override_rev7(mac, 0x1, value, core, off, 2);
299 bwn_nphy_rf_ctl_override_rev7(mac, 0x0800, 1, core, off, 1);
303 bwn_nphy_rf_ctl_override_rev7(mac, 0x0800, tmp, core, off, 0);
305 bwn_nphy_rf_ctl_override_rev7(mac, 0x6000, tmp, core, off, 0);
309 bwn_nphy_rf_ctl_override_rev7(mac, 0x1000, tmp, core, off, 0);
311 bwn_nphy_rf_ctl_override_rev7(mac, 0x4000, tmp, core, off, 0);
317 static void bwn_nphy_rf_ctl_override(struct bwn_mac *mac, uint16_t field,
326 BWN_ERRPRINTF(mac->mac_sc, "%s: field 0x%04x has >1 bit set\n",
331 if (mac->mac_phy.rev >= 3) {
335 BWN_ERRPRINTF(mac->mac_sc,
347 BWN_PHY_MASK(mac, en_addr, ~(field));
348 BWN_PHY_MASK(mac, val_addr,
352 BWN_PHY_SET(mac, en_addr, field);
353 BWN_PHY_SETMASK(mac, val_addr,
362 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~(field));
365 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_OVER, field);
370 BWN_ERRPRINTF(mac->mac_sc,
385 BWN_PHY_SETMASK(mac, addr, ~(rf_ctrl->bmask),
388 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_OVER, 0x1);
389 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD,
392 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, 0xFFFE);
397 static void bwn_nphy_rf_ctl_intc_override_rev7(struct bwn_mac *mac,
415 BWN_PHY_WRITE(mac, reg, 0);
416 BWN_PHY_MASK(mac, 0x2ff, ~0x2000);
417 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX);
420 BWN_PHY_SETMASK(mac, reg, ~0xC0, value << 6);
421 BWN_PHY_SET(mac, reg, 0x400);
423 BWN_PHY_MASK(mac, 0x2ff, ~0xC000 & 0xFFFF);
424 BWN_PHY_SET(mac, 0x2ff, 0x2000);
425 BWN_PHY_SET(mac, 0x2ff, 0x0001);
429 if (bwn_current_band(mac) == BWN_BAND_5G)
433 BWN_PHY_SETMASK(mac, reg, ~tmp, val);
434 BWN_PHY_SET(mac, reg, 0x1000);
437 if (bwn_current_band(mac) == BWN_BAND_5G) {
446 BWN_PHY_SETMASK(mac, reg, ~tmp, val);
447 BWN_PHY_MASK(mac, reg, ~tmp2);
450 if (bwn_current_band(mac) == BWN_BAND_5G) {
459 BWN_PHY_SETMASK(mac, reg, ~tmp, val);
460 BWN_PHY_MASK(mac, reg, ~tmp2);
467 static void bwn_nphy_rf_ctl_intc_override(struct bwn_mac *mac,
474 if (mac->mac_phy.rev >= 7) {
475 bwn_nphy_rf_ctl_intc_override_rev7(mac, intc_override, value,
480 if (mac->mac_phy.rev < 3) {
481 BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n",
483 mac->mac_phy.rev);
492 BWN_PHY_SET(mac, reg, 0x400);
496 BWN_PHY_WRITE(mac, reg, 0);
497 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX);
501 BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_INTC1,
503 BWN_PHY_SETMASK(mac, BWN_NPHY_TXF_40CO_B1S1,
505 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD,
508 if (!(BWN_PHY_READ(mac, BWN_NPHY_RFCTL_CMD) & BWN_NPHY_RFCTL_CMD_START)) {
515 BWN_ERRPRINTF(mac->mac_sc,
517 BWN_PHY_MASK(mac, BWN_NPHY_TXF_40CO_B1S1,
520 BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_INTC2,
522 BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_OVER,
524 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD,
527 if (!(BWN_PHY_READ(mac, BWN_NPHY_RFCTL_CMD) & BWN_NPHY_RFCTL_CMD_RXTX)) {
534 BWN_ERRPRINTF(mac->mac_sc,
536 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER,
541 if (bwn_current_band(mac) == BWN_BAND_5G) {
548 BWN_PHY_SETMASK(mac, reg, ~tmp, val);
551 if (bwn_current_band(mac) == BWN_BAND_5G) {
558 BWN_PHY_SETMASK(mac, reg, ~tmp, val);
561 if (bwn_current_band(mac) == BWN_BAND_5G) {
568 BWN_PHY_SETMASK(mac, reg, ~tmp, val);
579 static void bwn_nphy_write_clip_detection(struct bwn_mac *mac,
582 BWN_PHY_WRITE(mac, BWN_NPHY_C1_CLIP1THRES, clip_st[0]);
583 BWN_PHY_WRITE(mac, BWN_NPHY_C2_CLIP1THRES, clip_st[1]);
587 static void bwn_nphy_read_clip_detection(struct bwn_mac *mac, uint16_t *clip_st)
589 clip_st[0] = BWN_PHY_READ(mac, BWN_NPHY_C1_CLIP1THRES);
590 clip_st[1] = BWN_PHY_READ(mac, BWN_NPHY_C2_CLIP1THRES);
594 static uint16_t bwn_nphy_classifier(struct bwn_mac *mac, uint16_t mask, uint16_t val)
596 struct bwn_softc *sc = mac->mac_sc;
600 bwn_mac_suspend(mac);
602 tmp = BWN_PHY_READ(mac, BWN_NPHY_CLASSCTL);
607 BWN_PHY_SETMASK(mac, BWN_NPHY_CLASSCTL, 0xFFF8, tmp);
610 bwn_mac_enable(mac);
616 static void bwn_nphy_reset_cca(struct bwn_mac *mac)
620 bwn_phy_force_clock(mac, 1);
621 bbcfg = BWN_PHY_READ(mac, BWN_NPHY_BBCFG);
622 BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, bbcfg | BWN_NPHY_BBCFG_RSTCCA);
624 BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, bbcfg & ~BWN_NPHY_BBCFG_RSTCCA);
625 bwn_phy_force_clock(mac, 0);
626 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX);
630 static void bwn_nphy_stay_in_carrier_search(struct bwn_mac *mac, bool enable)
632 struct bwn_phy *phy = &mac->mac_phy;
638 nphy->classifier_state = bwn_nphy_classifier(mac, 0, 0);
639 bwn_nphy_classifier(mac, 0x7,
641 bwn_nphy_read_clip_detection(mac, nphy->clip_state);
642 bwn_nphy_write_clip_detection(mac, clip);
644 bwn_nphy_reset_cca(mac);
647 bwn_nphy_classifier(mac, 0x7, nphy->classifier_state);
648 bwn_nphy_write_clip_detection(mac, nphy->clip_state);
654 static uint16_t bwn_nphy_read_lpf_ctl(struct bwn_mac *mac, uint16_t offset)
657 offset = bwn_is_40mhz(mac) ? 0x159 : 0x154;
658 return bwn_ntab_read(mac, BWN_NTAB16(7, offset)) & 0x7;
662 static void bwn_nphy_adjust_lna_gain_table(struct bwn_mac *mac)
664 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
674 bwn_nphy_stay_in_carrier_search(mac, 1);
677 if (bwn_current_band(mac) == BWN_BAND_2G) {
681 tmp = 40370 - 315 * bwn_get_chan(mac);
683 tmp = 23242 - 224 * bwn_get_chan(mac);
703 bwn_ntab_write_bulk(mac, BWN_NTAB16(i, 8), 4, data);
708 BWN_PHY_SETMASK(mac, BWN_NPHY_C1_MINMAX_GAIN, ~BWN_NPHY_C1_MINGAIN,
710 BWN_PHY_SETMASK(mac, BWN_NPHY_C2_MINMAX_GAIN, ~BWN_NPHY_C2_MINGAIN,
714 bwn_nphy_stay_in_carrier_search(mac, 0);
718 static void bwn_nphy_set_rf_sequence(struct bwn_mac *mac, uint8_t cmd,
721 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
723 uint8_t end = (mac->mac_phy.rev >= 3) ? 0x1F : 0x0F;
728 bwn_nphy_stay_in_carrier_search(mac, true);
730 bwn_ntab_write_bulk(mac, BWN_NTAB8(7, offset1), length, events);
731 bwn_ntab_write_bulk(mac, BWN_NTAB8(7, offset2), length, delays);
734 bwn_ntab_write(mac, BWN_NTAB8(7, offset1 + i), end);
735 bwn_ntab_write(mac, BWN_NTAB8(7, offset2 + i), 1);
739 bwn_nphy_stay_in_carrier_search(mac, false);
746 static void bwn_radio_2057_chantab_upload(struct bwn_mac *mac,
751 BWN_RF_WRITE(mac, R2057_VCOCAL_COUNTVAL0, e_r7_2g->radio_vcocal_countval0);
752 BWN_RF_WRITE(mac, R2057_VCOCAL_COUNTVAL1, e_r7_2g->radio_vcocal_countval1);
753 BWN_RF_WRITE(mac, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7_2g->radio_rfpll_refmaster_sparextalsize);
754 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, e_r7_2g->radio_rfpll_loopfilter_r1);
755 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, e_r7_2g->radio_rfpll_loopfilter_c2);
756 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, e_r7_2g->radio_rfpll_loopfilter_c1);
757 BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, e_r7_2g->radio_cp_kpd_idac);
758 BWN_RF_WRITE(mac, R2057_RFPLL_MMD0, e_r7_2g->radio_rfpll_mmd0);
759 BWN_RF_WRITE(mac, R2057_RFPLL_MMD1, e_r7_2g->radio_rfpll_mmd1);
760 BWN_RF_WRITE(mac, R2057_VCOBUF_TUNE, e_r7_2g->radio_vcobuf_tune);
761 BWN_RF_WRITE(mac, R2057_LOGEN_MX2G_TUNE, e_r7_2g->radio_logen_mx2g_tune);
762 BWN_RF_WRITE(mac, R2057_LOGEN_INDBUF2G_TUNE, e_r7_2g->radio_logen_indbuf2g_tune);
763 BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7_2g->radio_txmix2g_tune_boost_pu_core0);
764 BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE0, e_r7_2g->radio_pad2g_tune_pus_core0);
765 BWN_RF_WRITE(mac, R2057_LNA2G_TUNE_CORE0, e_r7_2g->radio_lna2g_tune_core0);
766 BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7_2g->radio_txmix2g_tune_boost_pu_core1);
767 BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE1, e_r7_2g->radio_pad2g_tune_pus_core1);
768 BWN_RF_WRITE(mac, R2057_LNA2G_TUNE_CORE1, e_r7_2g->radio_lna2g_tune_core1);
771 BWN_RF_WRITE(mac, R2057_VCOCAL_COUNTVAL0, e_r7->radio_vcocal_countval0);
772 BWN_RF_WRITE(mac, R2057_VCOCAL_COUNTVAL1, e_r7->radio_vcocal_countval1);
773 BWN_RF_WRITE(mac, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7->radio_rfpll_refmaster_sparextalsize);
774 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, e_r7->radio_rfpll_loopfilter_r1);
775 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, e_r7->radio_rfpll_loopfilter_c2);
776 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, e_r7->radio_rfpll_loopfilter_c1);
777 BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, e_r7->radio_cp_kpd_idac);
778 BWN_RF_WRITE(mac, R2057_RFPLL_MMD0, e_r7->radio_rfpll_mmd0);
779 BWN_RF_WRITE(mac, R2057_RFPLL_MMD1, e_r7->radio_rfpll_mmd1);
780 BWN_RF_WRITE(mac, R2057_VCOBUF_TUNE, e_r7->radio_vcobuf_tune);
781 BWN_RF_WRITE(mac, R2057_LOGEN_MX2G_TUNE, e_r7->radio_logen_mx2g_tune);
782 BWN_RF_WRITE(mac, R2057_LOGEN_MX5G_TUNE, e_r7->radio_logen_mx5g_tune);
783 BWN_RF_WRITE(mac, R2057_LOGEN_INDBUF2G_TUNE, e_r7->radio_logen_indbuf2g_tune);
784 BWN_RF_WRITE(mac, R2057_LOGEN_INDBUF5G_TUNE, e_r7->radio_logen_indbuf5g_tune);
785 BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7->radio_txmix2g_tune_boost_pu_core0);
786 BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE0, e_r7->radio_pad2g_tune_pus_core0);
787 BWN_RF_WRITE(mac, R2057_PGA_BOOST_TUNE_CORE0, e_r7->radio_pga_boost_tune_core0);
788 BWN_RF_WRITE(mac, R2057_TXMIX5G_BOOST_TUNE_CORE0, e_r7->radio_txmix5g_boost_tune_core0);
789 BWN_RF_WRITE(mac, R2057_PAD5G_TUNE_MISC_PUS_CORE0, e_r7->radio_pad5g_tune_misc_pus_core0);
790 BWN_RF_WRITE(mac, R2057_LNA2G_TUNE_CORE0, e_r7->radio_lna2g_tune_core0);
791 BWN_RF_WRITE(mac, R2057_LNA5G_TUNE_CORE0, e_r7->radio_lna5g_tune_core0);
792 BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7->radio_txmix2g_tune_boost_pu_core1);
793 BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE1, e_r7->radio_pad2g_tune_pus_core1);
794 BWN_RF_WRITE(mac, R2057_PGA_BOOST_TUNE_CORE1, e_r7->radio_pga_boost_tune_core1);
795 BWN_RF_WRITE(mac, R2057_TXMIX5G_BOOST_TUNE_CORE1, e_r7->radio_txmix5g_boost_tune_core1);
796 BWN_RF_WRITE(mac, R2057_PAD5G_TUNE_MISC_PUS_CORE1, e_r7->radio_pad5g_tune_misc_pus_core1);
797 BWN_RF_WRITE(mac, R2057_LNA2G_TUNE_CORE1, e_r7->radio_lna2g_tune_core1);
798 BWN_RF_WRITE(mac, R2057_LNA5G_TUNE_CORE1, e_r7->radio_lna5g_tune_core1);
802 static void bwn_radio_2057_setup(struct bwn_mac *mac,
806 struct bwn_phy *phy = &mac->mac_phy;
808 bwn_radio_2057_chantab_upload(mac, tabent_r7, tabent_r7_2g);
813 if (bwn_current_band(mac) == BWN_BAND_2G) {
814 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, 0x3f);
815 BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, 0x3f);
816 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, 0x8);
817 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, 0x8);
819 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, 0x1f);
820 BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, 0x3f);
821 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, 0x8);
822 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, 0x8);
826 BWN_RF_WRITE(mac, R2057_LOGEN_PTAT_RESETS, 0x20);
827 BWN_RF_WRITE(mac, R2057_VCOBUF_IDACS, 0x18);
828 if (bwn_current_band(mac) == BWN_BAND_5G) {
829 BWN_RF_WRITE(mac, R2057_LOGEN_PTAT_RESETS, 0x38);
830 BWN_RF_WRITE(mac, R2057_VCOBUF_IDACS, 0x0f);
832 if (bwn_is_40mhz(mac)) {
835 BWN_RF_WRITE(mac,
838 BWN_RF_WRITE(mac,
845 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, 0x1b);
846 BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, 0x3f);
847 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, 0x1f);
848 BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, 0x1f);
852 if (bwn_current_band(mac) == BWN_BAND_2G) {
856 if (bwn_nphy_ipa(mac)) {
870 BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0,
873 BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE0,
876 BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1,
879 BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE1,
887 BWN_RF_MASK(mac, R2057_RFPLL_MISC_EN, ~0x01);
888 BWN_RF_MASK(mac, R2057_RFPLL_MISC_CAL_RESETN, ~0x04);
889 BWN_RF_SET(mac, R2057_RFPLL_MISC_CAL_RESETN, 0x4);
890 BWN_RF_SET(mac, R2057_RFPLL_MISC_EN, 0x01);
898 static uint8_t bwn_radio_2057_rcal(struct bwn_mac *mac)
900 struct bwn_phy *phy = &mac->mac_phy;
922 saved_regs_phy[i] = BWN_PHY_READ(mac, phy_to_store[i]);
924 saved_regs_phy_rf[i] = BWN_PHY_READ(mac, phy_to_store_rf[i]);
928 BWN_PHY_WRITE(mac, phy_to_store[i], 0);
929 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_RFCTL_OVER0, 0x07ff);
930 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_RFCTL_OVER1, 0x07ff);
931 BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER3, 0x07ff);
932 BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER4, 0x07ff);
933 BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER5, 0x007f);
934 BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER6, 0x007f);
938 BWN_PHY_MASK(mac, BWN_NPHY_REV7_RF_CTL_OVER3, ~0x2);
940 BWN_RF_SET(mac, R2057_IQTEST_SEL_PU, 0x1);
941 BWN_RF_SETMASK(mac, R2057v7_IQTEST_SEL_PU2, ~0x2, 0x1);
944 BWN_PHY_SET(mac, BWN_NPHY_REV7_RF_CTL_OVER3, 0x2);
945 BWN_PHY_SET(mac, BWN_NPHY_REV7_RF_CTL_MISC_REG3, 0x2);
946 saved_regs_radio[0] = BWN_RF_READ(mac, R2057_IQTEST_SEL_PU);
947 BWN_RF_WRITE(mac, R2057_IQTEST_SEL_PU, 0x11);
950 saved_regs_radio[0] = BWN_RF_READ(mac, R2057_IQTEST_SEL_PU);
951 saved_regs_radio[1] = BWN_RF_READ(mac, R2057v7_IQTEST_SEL_PU2);
952 BWN_PHY_SET(mac, BWN_NPHY_REV7_RF_CTL_MISC_REG3, 0x2);
953 BWN_PHY_SET(mac, BWN_NPHY_REV7_RF_CTL_OVER3, 0x2);
954 BWN_RF_WRITE(mac, R2057v7_IQTEST_SEL_PU2, 0x2);
955 BWN_RF_WRITE(mac, R2057_IQTEST_SEL_PU, 0x1);
960 BWN_RF_SET(mac, R2057_RCAL_CONFIG, 0x1);
964 BWN_RF_SET(mac, R2057_RCAL_CONFIG, 0x2);
969 BWN_RF_MASK(mac, R2057_RCAL_CONFIG, ~0x2);
972 if (!bwn_radio_wait_value(mac, R2057_RCAL_STATUS, 1, 1, 100, 1000000)) {
973 BWN_ERRPRINTF(mac->mac_sc, "Radio 0x2057 rcal timeout\n");
976 tmp = BWN_RF_READ(mac, R2057_RCAL_STATUS) & 0x3E;
979 BWN_RF_MASK(mac, R2057_RCAL_CONFIG, ~0x1);
983 BWN_PHY_WRITE(mac, phy_to_store_rf[i], saved_regs_phy_rf[i]);
985 BWN_PHY_WRITE(mac, phy_to_store[i], saved_regs_phy[i]);
990 BWN_RF_SETMASK(mac, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
991 BWN_RF_SETMASK(mac, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
995 BWN_RF_MASK(mac, R2057_IPA2G_CASCONV_CORE0, ~0x1);
996 BWN_RF_MASK(mac, R2057v7_IQTEST_SEL_PU2, ~0x2);
999 BWN_RF_WRITE(mac, R2057_IQTEST_SEL_PU, saved_regs_radio[0]);
1002 BWN_RF_WRITE(mac, R2057_IQTEST_SEL_PU, saved_regs_radio[0]);
1003 BWN_RF_WRITE(mac, R2057v7_IQTEST_SEL_PU2, saved_regs_radio[1]);
1013 static uint16_t bwn_radio_2057_rccal(struct bwn_mac *mac)
1015 struct bwn_phy *phy = &mac->mac_phy;
1022 BWN_RF_WRITE(mac, R2057_RCCAL_MASTER, 0x61);
1023 BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xC0);
1025 BWN_RF_WRITE(mac, R2057v7_RCCAL_MASTER, 0x61);
1026 BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xE9);
1028 BWN_RF_WRITE(mac, R2057_RCCAL_X1, 0x6E);
1031 BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x55);
1032 if (!bwn_radio_wait_value(mac, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
1034 BWN_DBGPRINTF(mac, "Radio 0x2057 rccal timeout\n");
1037 BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x15);
1043 BWN_RF_WRITE(mac, R2057_RCCAL_MASTER, 0x69);
1044 BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xB0);
1046 BWN_RF_WRITE(mac, R2057v7_RCCAL_MASTER, 0x69);
1047 BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xD5);
1049 BWN_RF_WRITE(mac, R2057_RCCAL_X1, 0x6E);
1054 BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x55);
1057 if (!bwn_radio_wait_value(mac, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
1059 BWN_DBGPRINTF(mac, "Radio 0x2057 rccal timeout\n");
1062 BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x15);
1068 BWN_RF_WRITE(mac, R2057_RCCAL_MASTER, 0x73);
1069 BWN_RF_WRITE(mac, R2057_RCCAL_X1, 0x28);
1070 BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xB0);
1072 BWN_RF_WRITE(mac, R2057v7_RCCAL_MASTER, 0x73);
1073 BWN_RF_WRITE(mac, R2057_RCCAL_X1, 0x6E);
1074 BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0x99);
1080 BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x55);
1083 if (!bwn_radio_wait_value(mac, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500,
1085 BWN_ERRPRINTF(mac->mac_sc, "Radio 0x2057 rcal timeout\n");
1088 tmp = BWN_RF_READ(mac, R2057_RCCAL_DONE_OSCCAP);
1091 BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x15);
1096 BWN_RF_MASK(mac, R2057_RCCAL_MASTER, ~0x1);
1098 BWN_RF_MASK(mac, R2057v7_RCCAL_MASTER, ~0x1);
1103 static void bwn_radio_2057_init_pre(struct bwn_mac *mac)
1105 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, ~BWN_NPHY_RFCTL_CMD_CHIP0PU);
1107 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_OEPORFORCE);
1108 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, ~BWN_NPHY_RFCTL_CMD_OEPORFORCE);
1109 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_CHIP0PU);
1112 static void bwn_radio_2057_init_post(struct bwn_mac *mac)
1114 BWN_RF_SET(mac, R2057_XTALPUOVR_PINCTRL, 0x1);
1117 BWN_RF_SET(mac, R2057_XTALPUOVR_PINCTRL, 0x2);
1119 BWN_RF_SET(mac, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
1120 BWN_RF_SET(mac, R2057_XTAL_CONFIG2, 0x80);
1122 BWN_RF_MASK(mac, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
1123 BWN_RF_MASK(mac, R2057_XTAL_CONFIG2, ~0x80);
1125 if (mac->mac_phy.phy_do_full_init) {
1126 bwn_radio_2057_rcal(mac);
1127 bwn_radio_2057_rccal(mac);
1129 BWN_RF_MASK(mac, R2057_RFPLL_MASTER, ~0x8);
1133 static void bwn_radio_2057_init(struct bwn_mac *mac)
1135 bwn_radio_2057_init_pre(mac);
1136 r2057_upload_inittabs(mac);
1137 bwn_radio_2057_init_post(mac);
1144 static void bwn_chantab_radio_2056_upload(struct bwn_mac *mac,
1147 BWN_RF_WRITE(mac, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
1148 BWN_RF_WRITE(mac, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
1149 BWN_RF_WRITE(mac, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
1150 BWN_RF_WRITE(mac, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
1151 BWN_RF_WRITE(mac, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
1152 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1,
1154 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2,
1156 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER3,
1158 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4,
1160 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER5,
1162 BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR27,
1164 BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR28,
1166 BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR29,
1168 BWN_RF_WRITE(mac, B2056_SYN_LOGEN_VCOBUF1,
1170 BWN_RF_WRITE(mac, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
1171 BWN_RF_WRITE(mac, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
1172 BWN_RF_WRITE(mac, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
1174 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_LNAA_TUNE,
1176 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_LNAG_TUNE,
1179 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
1181 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
1183 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
1185 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
1187 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
1189 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
1191 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
1193 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
1196 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_LNAA_TUNE,
1198 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_LNAG_TUNE,
1201 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
1203 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
1205 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
1207 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
1209 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
1211 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
1213 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
1215 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
1220 static void bwn_radio_2056_setup(struct bwn_mac *mac,
1223 struct bwn_softc *sc = mac->mac_sc;
1224 bwn_band_t band = bwn_current_band(mac);
1232 DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__);
1234 if (mac->mac_phy.rev < 3) {
1235 BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n",
1237 mac->mac_phy.rev);
1246 bwn_chantab_radio_2056_upload(mac, e);
1247 b2056_upload_syn_pll_cp2(mac, band == BWN_BAND_5G);
1250 bwn_current_band(mac) == BWN_BAND_2G) {
1251 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
1252 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
1255 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x14);
1256 BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0);
1258 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
1259 BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0x14);
1263 bwn_current_band(mac) == BWN_BAND_2G) {
1264 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, 0x1f);
1265 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, 0x1f);
1266 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x0b);
1267 BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0x20);
1270 bwn_current_band(mac) == BWN_BAND_5G) {
1271 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
1272 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
1273 BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x05);
1274 BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0x0C);
1277 if (mac->mac_phy.phy_n->ipa2g_on && band == BWN_BAND_2G) {
1280 if (mac->mac_phy.rev >= 5) {
1281 BWN_RF_WRITE(mac,
1304 BWN_RF_WRITE(mac,
1307 BWN_RF_WRITE(mac,
1310 BWN_RF_WRITE(mac,
1313 BWN_RF_WRITE(mac,
1316 BWN_RF_WRITE(mac,
1319 BWN_RF_WRITE(mac,
1322 BWN_RF_WRITE(mac,
1326 bias = bwn_is_40mhz(mac) ? 0x40 : 0x20;
1327 BWN_RF_WRITE(mac,
1330 BWN_RF_WRITE(mac,
1333 BWN_RF_WRITE(mac,
1337 BWN_RF_WRITE(mac, offset | B2056_TX_PA_SPARE1, 0xee);
1339 } else if (mac->mac_phy.phy_n->ipa5g_on && band == BWN_BAND_5G) {
1340 uint16_t freq = bwn_get_centre_freq(mac);
1372 BWN_RF_WRITE(mac,
1374 BWN_RF_WRITE(mac,
1376 BWN_RF_WRITE(mac,
1378 BWN_RF_WRITE(mac,
1380 BWN_RF_WRITE(mac,
1382 BWN_RF_WRITE(mac,
1384 BWN_RF_WRITE(mac,
1386 BWN_RF_WRITE(mac,
1388 BWN_RF_WRITE(mac,
1390 BWN_RF_WRITE(mac,
1397 BWN_RF_WRITE(mac, B2056_SYN_PLL_VCOCAL12, 0x00);
1398 BWN_RF_WRITE(mac, B2056_TX_INTPAA_PA_MISC, 0x38);
1399 BWN_RF_WRITE(mac, B2056_TX_INTPAA_PA_MISC, 0x18);
1400 BWN_RF_WRITE(mac, B2056_TX_INTPAA_PA_MISC, 0x38);
1401 BWN_RF_WRITE(mac, B2056_TX_INTPAA_PA_MISC, 0x39);
1405 static uint8_t bwn_radio_2056_rcal(struct bwn_mac *mac)
1407 struct bwn_phy *phy = &mac->mac_phy;
1412 DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__);
1414 mast2 = BWN_RF_READ(mac, B2056_SYN_PLL_MAST2);
1415 BWN_RF_WRITE(mac, B2056_SYN_PLL_MAST2, mast2 | 0x7);
1418 BWN_RF_WRITE(mac, B2056_SYN_RCAL_MASTER, 0x01);
1420 BWN_RF_WRITE(mac, B2056_SYN_RCAL_MASTER, 0x09);
1422 if (!bwn_radio_wait_value(mac, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
1424 BWN_ERRPRINTF(mac->mac_sc, "Radio recalibration timeout\n");
1428 BWN_RF_WRITE(mac, B2056_SYN_RCAL_MASTER, 0x01);
1429 tmp = BWN_RF_READ(mac, B2056_SYN_RCAL_CODE_OUT);
1430 BWN_RF_WRITE(mac, B2056_SYN_RCAL_MASTER, 0x00);
1432 BWN_RF_WRITE(mac, B2056_SYN_PLL_MAST2, mast2);
1437 static void bwn_radio_init2056_pre(struct bwn_mac *mac)
1439 DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__);
1441 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD,
1444 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD,
1446 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD,
1448 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD,
1452 static void bwn_radio_init2056_post(struct bwn_mac *mac)
1454 DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__);
1456 BWN_RF_SET(mac, B2056_SYN_COM_CTRL, 0xB);
1457 BWN_RF_SET(mac, B2056_SYN_COM_PU, 0x2);
1458 BWN_RF_SET(mac, B2056_SYN_COM_RESET, 0x2);
1460 BWN_RF_MASK(mac, B2056_SYN_COM_RESET, ~0x2);
1461 BWN_RF_MASK(mac, B2056_SYN_PLL_MAST2, ~0xFC);
1462 BWN_RF_MASK(mac, B2056_SYN_RCCAL_CTRL0, ~0x1);
1463 if (mac->mac_phy.phy_do_full_init)
1464 bwn_radio_2056_rcal(mac);
1471 static void bwn_radio_init2056(struct bwn_mac *mac)
1473 DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__);
1475 bwn_radio_init2056_pre(mac);
1476 b2056_upload_inittabs(mac, 0, 0);
1477 bwn_radio_init2056_post(mac);
1484 static void bwn_chantab_radio_upload(struct bwn_mac *mac,
1487 BWN_RF_WRITE(mac, B2055_PLL_REF, e->radio_pll_ref);
1488 BWN_RF_WRITE(mac, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
1489 BWN_RF_WRITE(mac, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
1490 BWN_RF_WRITE(mac, B2055_VCO_CAPTAIL, e->radio_vco_captail);
1491 BWN_READ_4(mac, BWN_MACCTL); /* flush writes */
1493 BWN_RF_WRITE(mac, B2055_VCO_CAL1, e->radio_vco_cal1);
1494 BWN_RF_WRITE(mac, B2055_VCO_CAL2, e->radio_vco_cal2);
1495 BWN_RF_WRITE(mac, B2055_PLL_LFC1, e->radio_pll_lfc1);
1496 BWN_RF_WRITE(mac, B2055_PLL_LFR1, e->radio_pll_lfr1);
1497 BWN_READ_4(mac, BWN_MACCTL); /* flush writes */
1499 BWN_RF_WRITE(mac, B2055_PLL_LFC2, e->radio_pll_lfc2);
1500 BWN_RF_WRITE(mac, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
1501 BWN_RF_WRITE(mac, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
1502 BWN_RF_WRITE(mac, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
1503 BWN_READ_4(mac, BWN_MACCTL); /* flush writes */
1505 BWN_RF_WRITE(mac, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
1506 BWN_RF_WRITE(mac, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
1507 BWN_RF_WRITE(mac, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
1508 BWN_RF_WRITE(mac, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
1509 BWN_READ_4(mac, BWN_MACCTL); /* flush writes */
1511 BWN_RF_WRITE(mac, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
1512 BWN_RF_WRITE(mac, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
1513 BWN_RF_WRITE(mac, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
1514 BWN_RF_WRITE(mac, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
1515 BWN_READ_4(mac, BWN_MACCTL); /* flush writes */
1517 BWN_RF_WRITE(mac, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
1518 BWN_RF_WRITE(mac, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
1522 static void bwn_radio_2055_setup(struct bwn_mac *mac,
1526 if (mac->mac_phy.rev >= 3) {
1527 BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n",
1529 mac->mac_phy.rev);
1532 DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__);
1534 bwn_chantab_radio_upload(mac, e);
1536 BWN_RF_WRITE(mac, B2055_VCO_CAL10, 0x05);
1537 BWN_RF_WRITE(mac, B2055_VCO_CAL10, 0x45);
1538 BWN_READ_4(mac, BWN_MACCTL); /* flush writes */
1539 BWN_RF_WRITE(mac, B2055_VCO_CAL10, 0x65);
1543 static void bwn_radio_init2055_pre(struct bwn_mac *mac)
1545 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD,
1547 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD,
1550 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD,
1554 static void bwn_radio_init2055_post(struct bwn_mac *mac)
1556 struct bwn_softc *sc = mac->mac_sc;
1557 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
1569 BWN_RF_MASK(mac, B2055_MASTER1, 0xFFF3);
1571 BWN_RF_MASK(mac, B2055_C1_RX_BB_REG, 0x7F);
1572 BWN_RF_MASK(mac, B2055_C2_RX_BB_REG, 0x7F);
1574 BWN_RF_SETMASK(mac, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1575 BWN_RF_WRITE(mac, B2055_CAL_MISC, 0x3C);
1576 BWN_RF_MASK(mac, B2055_CAL_MISC, 0xFFBE);
1577 BWN_RF_SET(mac, B2055_CAL_LPOCTL, 0x80);
1578 BWN_RF_SET(mac, B2055_CAL_MISC, 0x1);
1580 BWN_RF_SET(mac, B2055_CAL_MISC, 0x40);
1581 if (!bwn_radio_wait_value(mac, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
1582 BWN_ERRPRINTF(mac->mac_sc, "radio post init timeout\n");
1583 BWN_RF_MASK(mac, B2055_CAL_LPOCTL, 0xFF7F);
1584 bwn_switch_channel(mac, bwn_get_chan(mac));
1585 BWN_RF_WRITE(mac, B2055_C1_RX_BB_LPF, 0x9);
1586 BWN_RF_WRITE(mac, B2055_C2_RX_BB_LPF, 0x9);
1587 BWN_RF_WRITE(mac, B2055_C1_RX_BB_MIDACHP, 0x83);
1588 BWN_RF_WRITE(mac, B2055_C2_RX_BB_MIDACHP, 0x83);
1589 BWN_RF_SETMASK(mac, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1590 BWN_RF_SETMASK(mac, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1592 BWN_RF_SET(mac, B2055_C1_RX_RFSPC1, 0x2);
1593 BWN_RF_SET(mac, B2055_C2_RX_RFSPC1, 0x2);
1595 BWN_RF_MASK(mac, B2055_C1_RX_RFSPC1, 0xFFFD);
1596 BWN_RF_MASK(mac, B2055_C2_RX_RFSPC1, 0xFFFD);
1605 static void bwn_radio_init2055(struct bwn_mac *mac)
1607 bwn_radio_init2055_pre(mac);
1608 if (mac->mac_status < BWN_MAC_STATUS_INITED) {
1610 b2055_upload_inittab(mac, 0, 0);
1612 bool ghz5 = bwn_current_band(mac) == BWN_BAND_5G;
1613 b2055_upload_inittab(mac, ghz5, 0);
1615 bwn_radio_init2055_post(mac);
1623 static int bwn_nphy_load_samples(struct bwn_mac *mac,
1625 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
1631 BWN_ERRPRINTF(mac->mac_sc, "allocation for samples loading failed\n");
1635 bwn_nphy_stay_in_carrier_search(mac, 1);
1641 bwn_ntab_write_bulk(mac, BWN_NTAB32(17, 0), len, data);
1645 bwn_nphy_stay_in_carrier_search(mac, 0);
1650 static uint16_t bwn_nphy_gen_load_samples(struct bwn_mac *mac, uint32_t freq, uint16_t max,
1657 bw = bwn_is_40mhz(mac) ? 40 : 20;
1661 if (BWN_PHY_READ(mac, BWN_NPHY_BBCFG) & BWN_NPHY_BBCFG_RSTRX)
1666 if (bwn_is_40mhz(mac))
1674 BWN_ERRPRINTF(mac->mac_sc, "allocation for samples generation failed\n");
1687 i = bwn_nphy_load_samples(mac, samples, len);
1693 static void bwn_nphy_run_samples(struct bwn_mac *mac, uint16_t samps, uint16_t loops,
1697 struct bwn_phy *phy = &mac->mac_phy;
1698 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
1703 bwn_nphy_stay_in_carrier_search(mac, true);
1708 lpf_bw3 = BWN_PHY_READ(mac, BWN_NPHY_REV7_RF_CTL_OVER3) & 0x80;
1709 lpf_bw4 = BWN_PHY_READ(mac, BWN_NPHY_REV7_RF_CTL_OVER4) & 0x80;
1714 uint16_t value = bwn_nphy_read_lpf_ctl(mac, 0);
1716 bwn_nphy_rf_ctl_override_rev19(mac, 0x80, value,
1719 bwn_nphy_rf_ctl_override_rev7(mac, 0x80, value,
1726 tmp = bwn_ntab_read(mac, BWN_NTAB16(15, 87));
1731 tmp = !bwn_is_40mhz(mac) ? 0x6464 : 0x4747;
1732 bwn_ntab_write(mac, BWN_NTAB16(15, 87), tmp);
1735 BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_DEPCNT, (samps - 1));
1738 BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_LOOPCNT, (loops - 1));
1740 BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_LOOPCNT, loops);
1742 BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_WAITCNT, wait);
1744 seq_mode = BWN_PHY_READ(mac, BWN_NPHY_RFSEQMODE);
1746 BWN_PHY_SET(mac, BWN_NPHY_RFSEQMODE, BWN_NPHY_RFSEQMODE_CAOVER);
1748 BWN_PHY_MASK(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1749 BWN_PHY_SET(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1752 BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_CMD, tmp);
1755 if (!(BWN_PHY_READ(mac, BWN_NPHY_RFSEQST) & 1)) {
1762 BWN_ERRPRINTF(mac->mac_sc, "run samples timeout\n");
1764 BWN_PHY_WRITE(mac, BWN_NPHY_RFSEQMODE, seq_mode);
1766 bwn_nphy_stay_in_carrier_search(mac, false);
1774 static void bwn_nphy_scale_offset_rssi(struct bwn_mac *mac, uint16_t scale,
1789 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1791 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1793 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1795 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1799 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_X, tmp);
1801 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1803 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_X, tmp);
1805 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1809 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1811 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1813 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1815 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1819 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_TBD, tmp);
1821 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_TBD, tmp);
1823 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_TBD, tmp);
1825 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_TBD, tmp);
1829 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_PWRDET, tmp);
1831 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_PWRDET, tmp);
1833 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_PWRDET, tmp);
1835 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_PWRDET, tmp);
1839 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_TSSI, tmp);
1841 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_TSSI, tmp);
1845 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_TSSI, tmp);
1847 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_TSSI, tmp);
1852 static void bwn_nphy_rssi_select_rev19(struct bwn_mac *mac, uint8_t code,
1858 static void bwn_nphy_rev3_rssi_select(struct bwn_mac *mac, uint8_t code,
1865 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER1, 0xFDFF);
1866 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, 0xFDFF);
1867 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C1, 0xFCFF);
1868 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C2, 0xFCFF);
1869 BWN_PHY_MASK(mac, BWN_NPHY_TXF_40CO_B1S0, 0xFFDF);
1870 BWN_PHY_MASK(mac, BWN_NPHY_TXF_40CO_B32S1, 0xFFDF);
1871 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1872 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1880 BWN_PHY_SETMASK(mac, reg, 0xFDFF, 0x0200);
1888 BWN_PHY_SETMASK(mac, reg, 0xFCFF, 0);
1893 BWN_PHY_SETMASK(mac, reg, 0xFFC3, 0);
1896 val = (bwn_current_band(mac) == BWN_BAND_5G) ? 4 : 8;
1901 BWN_PHY_SET(mac, reg, val);
1906 BWN_PHY_SET(mac, reg, 0x0020);
1919 BWN_PHY_SETMASK(mac, reg, 0xFCFF, val);
1920 BWN_PHY_SETMASK(mac, reg, 0xF3FF, val << 2);
1925 bwn_current_band(mac);
1927 if (mac->mac_phy.rev < 7) {
1928 if (bwn_nphy_ipa(mac))
1934 BWN_RF_WRITE(mac, reg, val);
1940 BWN_PHY_SET(mac, reg, 0x0200);
1947 static void bwn_nphy_rev2_rssi_select(struct bwn_mac *mac, uint8_t code,
1971 BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C1, 0x0FFF, val);
1972 BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C2, 0x0FFF, val);
1975 BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_RSSIO1, 0xFFCF,
1977 BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_RSSIO2, 0xFFCF,
1982 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, ~0x3000);
1984 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD,
1987 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER,
1992 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD,
1995 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~0x1);
1998 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x3000);
2000 BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_CMD,
2005 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_OVER,
2010 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD,
2013 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~0x1);
2019 static void bwn_nphy_rssi_select(struct bwn_mac *mac, uint8_t code,
2022 if (mac->mac_phy.rev >= 19)
2023 bwn_nphy_rssi_select_rev19(mac, code, type);
2024 else if (mac->mac_phy.rev >= 3)
2025 bwn_nphy_rev3_rssi_select(mac, code, type);
2027 bwn_nphy_rev2_rssi_select(mac, code, type);
2031 static void bwn_nphy_set_rssi_2055_vcm(struct bwn_mac *mac,
2038 BWN_RF_SETMASK(mac, B2055_C1_B0NB_RSSIVCM,
2040 BWN_RF_SETMASK(mac, B2055_C1_RX_BB_RSSICTL5,
2043 BWN_RF_SETMASK(mac, B2055_C2_B0NB_RSSIVCM,
2045 BWN_RF_SETMASK(mac, B2055_C2_RX_BB_RSSICTL5,
2050 BWN_RF_SETMASK(mac, B2055_C1_RX_BB_RSSICTL5,
2053 BWN_RF_SETMASK(mac, B2055_C2_RX_BB_RSSICTL5,
2060 static int bwn_nphy_poll_rssi(struct bwn_mac *mac, enum n_rssi_type rssi_type,
2070 if (mac->mac_phy.rev >= 3) {
2071 save_regs_phy[0] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C1);
2072 save_regs_phy[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C2);
2073 save_regs_phy[2] = BWN_PHY_READ(mac,
2075 save_regs_phy[3] = BWN_PHY_READ(mac,
2077 save_regs_phy[4] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER1);
2078 save_regs_phy[5] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER);
2079 save_regs_phy[6] = BWN_PHY_READ(mac, BWN_NPHY_TXF_40CO_B1S0);
2080 save_regs_phy[7] = BWN_PHY_READ(mac, BWN_NPHY_TXF_40CO_B32S1);
2083 save_regs_phy[0] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C1);
2084 save_regs_phy[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C2);
2085 save_regs_phy[2] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER);
2086 save_regs_phy[3] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_CMD);
2087 save_regs_phy[4] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_OVER);
2088 save_regs_phy[5] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_RSSIO1);
2089 save_regs_phy[6] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_RSSIO2);
2094 bwn_nphy_rssi_select(mac, 5, rssi_type);
2096 if (mac->mac_phy.rev < 2) {
2097 save_regs_phy[8] = BWN_PHY_READ(mac, BWN_NPHY_GPIO_SEL);
2098 BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_SEL, 5);
2105 if (mac->mac_phy.rev < 2) {
2106 s[0] = BWN_PHY_READ(mac, BWN_NPHY_GPIO_LOOUT);
2107 s[1] = BWN_PHY_READ(mac, BWN_NPHY_GPIO_HIOUT);
2109 s[0] = BWN_PHY_READ(mac, BWN_NPHY_RSSI1);
2110 s[1] = BWN_PHY_READ(mac, BWN_NPHY_RSSI2);
2121 if (mac->mac_phy.rev < 2)
2122 BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_SEL, save_regs_phy[8]);
2124 if (mac->mac_phy.rev >= 3) {
2125 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, save_regs_phy[0]);
2126 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, save_regs_phy[1]);
2127 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1,
2129 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2,
2131 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2132 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, save_regs_phy[5]);
2133 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2134 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2136 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, save_regs_phy[0]);
2137 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, save_regs_phy[1]);
2138 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, save_regs_phy[2]);
2139 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_CMD, save_regs_phy[3]);
2140 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_OVER, save_regs_phy[4]);
2141 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2142 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2149 static void bwn_nphy_rev3_rssi_cal(struct bwn_mac *mac)
2151 //struct bwn_phy *phy = &mac->mac_phy;
2152 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
2200 if (mac->mac_phy.rev >= 7) {
2212 class = bwn_nphy_classifier(mac, 0, 0);
2213 bwn_nphy_classifier(mac, 7, 4);
2214 bwn_nphy_read_clip_detection(mac, clip_state);
2215 bwn_nphy_write_clip_detection(mac, clip_off);
2217 saved_regs_phy_rfctl[0] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1);
2218 saved_regs_phy_rfctl[1] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2);
2220 saved_regs_phy[i] = BWN_PHY_READ(mac, regs_to_store[i]);
2222 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_OFF, 0, 7);
2223 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, 1, 7);
2225 if (mac->mac_phy.rev >= 7) {
2226 bwn_nphy_rf_ctl_override_one_to_many(mac,
2229 bwn_nphy_rf_ctl_override_one_to_many(mac,
2232 bwn_nphy_rf_ctl_override_rev7(mac, 0x80, 1, 0, false, 0);
2233 bwn_nphy_rf_ctl_override_rev7(mac, 0x40, 1, 0, false, 0);
2234 if (bwn_current_band(mac) == BWN_BAND_5G) {
2235 bwn_nphy_rf_ctl_override_rev7(mac, 0x20, 0, 0, false,
2237 bwn_nphy_rf_ctl_override_rev7(mac, 0x10, 1, 0, false,
2240 bwn_nphy_rf_ctl_override_rev7(mac, 0x10, 0, 0, false,
2242 bwn_nphy_rf_ctl_override_rev7(mac, 0x20, 1, 0, false,
2246 bwn_nphy_rf_ctl_override(mac, 0x1, 0, 0, false);
2247 bwn_nphy_rf_ctl_override(mac, 0x2, 1, 0, false);
2248 bwn_nphy_rf_ctl_override(mac, 0x80, 1, 0, false);
2249 bwn_nphy_rf_ctl_override(mac, 0x40, 1, 0, false);
2250 if (bwn_current_band(mac) == BWN_BAND_5G) {
2251 bwn_nphy_rf_ctl_override(mac, 0x20, 0, 0, false);
2252 bwn_nphy_rf_ctl_override(mac, 0x10, 1, 0, false);
2254 bwn_nphy_rf_ctl_override(mac, 0x10, 0, 0, false);
2255 bwn_nphy_rf_ctl_override(mac, 0x20, 1, 0, false);
2259 rx_core_state = bwn_nphy_get_rx_core_state(mac);
2264 bwn_nphy_scale_offset_rssi(mac, 0, 0, core + 1, N_RAIL_I,
2266 bwn_nphy_scale_offset_rssi(mac, 0, 0, core + 1, N_RAIL_Q,
2271 if (mac->mac_phy.rev >= 7)
2272 BWN_RF_SETMASK(mac,
2277 BWN_RF_SETMASK(mac, r | B2056_RX_RSSI_MISC,
2279 bwn_nphy_poll_rssi(mac, N_RSSI_NB, results[vcm], 8);
2305 if (mac->mac_phy.rev >= 7)
2306 BWN_RF_SETMASK(mac,
2311 BWN_RF_SETMASK(mac, r | B2056_RX_RSSI_MISC,
2324 bwn_nphy_scale_offset_rssi(mac, 0, offset[i],
2335 bwn_nphy_scale_offset_rssi(mac, 0, 0, core + 1,
2337 bwn_nphy_scale_offset_rssi(mac, 0, 0, core + 1,
2339 bwn_nphy_poll_rssi(mac, i, poll_results, 8);
2347 bwn_nphy_scale_offset_rssi(mac, 0,
2354 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
2355 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
2357 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX);
2359 BWN_PHY_SET(mac, BWN_NPHY_TXF_40CO_B1S1, 0x1);
2360 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_START);
2361 BWN_PHY_MASK(mac, BWN_NPHY_TXF_40CO_B1S1, ~0x1);
2363 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_OVER, 0x1);
2364 BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_RXTX);
2365 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~0x1);
2368 BWN_PHY_WRITE(mac, regs_to_store[i], saved_regs_phy[i]);
2371 if (bwn_current_band(mac) == BWN_BAND_2G) {
2378 if (mac->mac_phy.rev >= 7) {
2379 rssical_radio_regs[0] = BWN_RF_READ(mac,
2381 rssical_radio_regs[1] = BWN_RF_READ(mac,
2384 rssical_radio_regs[0] = BWN_RF_READ(mac, B2056_RX0 |
2386 rssical_radio_regs[1] = BWN_RF_READ(mac, B2056_RX1 |
2389 rssical_phy_regs[0] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0I_RSSI_Z);
2390 rssical_phy_regs[1] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Z);
2391 rssical_phy_regs[2] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1I_RSSI_Z);
2392 rssical_phy_regs[3] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Z);
2393 rssical_phy_regs[4] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0I_RSSI_X);
2394 rssical_phy_regs[5] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0Q_RSSI_X);
2395 rssical_phy_regs[6] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1I_RSSI_X);
2396 rssical_phy_regs[7] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1Q_RSSI_X);
2397 rssical_phy_regs[8] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0I_RSSI_Y);
2398 rssical_phy_regs[9] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Y);
2399 rssical_phy_regs[10] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1I_RSSI_Y);
2400 rssical_phy_regs[11] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Y);
2403 if (bwn_current_band(mac) == BWN_BAND_2G)
2404 nphy->rssical_chanspec_2G.center_freq = bwn_get_centre_freq(mac);
2406 nphy->rssical_chanspec_5G.center_freq = bwn_get_centre_freq(mac);
2409 bwn_nphy_classifier(mac, 7, class);
2410 bwn_nphy_write_clip_detection(mac, clip_state);
2414 static void bwn_nphy_rev2_rssi_cal(struct bwn_mac *mac, enum n_rssi_type type)
2441 BWN_ERRPRINTF(mac->mac_sc, "%s: RSSI type %d invalid\n",
2447 class = bwn_nphy_classifier(mac, 0, 0);
2448 bwn_nphy_classifier(mac, 7, 4);
2449 bwn_nphy_read_clip_detection(mac, clip_state);
2450 bwn_nphy_write_clip_detection(mac, clip_off);
2452 if (bwn_current_band(mac) == BWN_BAND_5G)
2457 regs_save_phy[0] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1);
2458 regs_save_radio[0] = BWN_RF_READ(mac, B2055_C1_PD_RXTX);
2459 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, override);
2460 BWN_RF_WRITE(mac, B2055_C1_PD_RXTX, val);
2462 regs_save_phy[1] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2);
2463 regs_save_radio[1] = BWN_RF_READ(mac, B2055_C2_PD_RXTX);
2464 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, override);
2465 BWN_RF_WRITE(mac, B2055_C2_PD_RXTX, val);
2467 state[0] = BWN_RF_READ(mac, B2055_C1_PD_RSSIMISC) & 0x07;
2468 state[1] = BWN_RF_READ(mac, B2055_C2_PD_RSSIMISC) & 0x07;
2469 BWN_RF_MASK(mac, B2055_C1_PD_RSSIMISC, 0xF8);
2470 BWN_RF_MASK(mac, B2055_C2_PD_RSSIMISC, 0xF8);
2471 state[2] = BWN_RF_READ(mac, B2055_C1_SP_RSSI) & 0x07;
2472 state[3] = BWN_RF_READ(mac, B2055_C2_SP_RSSI) & 0x07;
2474 bwn_nphy_rssi_select(mac, 5, type);
2475 bwn_nphy_scale_offset_rssi(mac, 0, 0, 5, N_RAIL_I, type);
2476 bwn_nphy_scale_offset_rssi(mac, 0, 0, 5, N_RAIL_Q, type);
2483 bwn_nphy_set_rssi_2055_vcm(mac, type, tmp);
2484 bwn_nphy_poll_rssi(mac, type, results[vcm], 8);
2515 bwn_nphy_set_rssi_2055_vcm(mac, type, vcm_final);
2531 bwn_nphy_scale_offset_rssi(mac, 0, offset[i], core, rail,
2535 BWN_RF_SETMASK(mac, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2536 BWN_RF_SETMASK(mac, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2540 bwn_nphy_rssi_select(mac, 1, N_RSSI_NB);
2543 bwn_nphy_rssi_select(mac, 1, N_RSSI_W1);
2546 bwn_nphy_rssi_select(mac, 1, N_RSSI_W2);
2549 bwn_nphy_rssi_select(mac, 1, N_RSSI_W2);
2555 bwn_nphy_rssi_select(mac, 2, N_RSSI_NB);
2558 bwn_nphy_rssi_select(mac, 2, N_RSSI_W1);
2561 bwn_nphy_rssi_select(mac, 2, N_RSSI_W2);
2565 bwn_nphy_rssi_select(mac, 0, type);
2567 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2568 BWN_RF_WRITE(mac, B2055_C1_PD_RXTX, regs_save_radio[0]);
2569 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2570 BWN_RF_WRITE(mac, B2055_C2_PD_RXTX, regs_save_radio[1]);
2572 bwn_nphy_classifier(mac, 7, class);
2573 bwn_nphy_write_clip_detection(mac, clip_state);
2576 bwn_nphy_reset_cca(mac);
2583 static void bwn_nphy_rssi_cal(struct bwn_mac *mac)
2585 if (mac->mac_phy.rev >= 19) {
2587 } else if (mac->mac_phy.rev >= 3) {
2588 bwn_nphy_rev3_rssi_cal(mac);
2590 bwn_nphy_rev2_rssi_cal(mac, N_RSSI_NB);
2591 bwn_nphy_rev2_rssi_cal(mac, N_RSSI_W1);
2592 bwn_nphy_rev2_rssi_cal(mac, N_RSSI_W2);
2600 static void bwn_nphy_gain_ctl_workarounds_rev19(struct bwn_mac *mac)
2605 static void bwn_nphy_gain_ctl_workarounds_rev7(struct bwn_mac *mac)
2607 struct bwn_phy *phy = &mac->mac_phy;
2614 static void bwn_nphy_gain_ctl_workarounds_rev3(struct bwn_mac *mac)
2616 struct bwn_softc *sc = mac->mac_sc;
2625 ghz5 = BWN_PHY_READ(mac, BWN_NPHY_BANDCTL)
2629 e = bwn_nphy_get_gain_ctl_workaround_ent(mac, ghz5, ext_lna);
2630 if (ghz5 && mac->mac_phy.rev >= 5)
2635 BWN_PHY_SET(mac, BWN_NPHY_RXCTL, 0x0040);
2638 BWN_PHY_SET(mac, BWN_NPHY_C1_CGAINI, BWN_NPHY_C1_CGAINI_CL2DETECT);
2639 BWN_PHY_SET(mac, BWN_NPHY_C2_CGAINI, BWN_NPHY_C2_CGAINI_CL2DETECT);
2641 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2643 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2645 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
2646 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
2647 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
2648 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
2649 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_RSSI_GAIN,
2651 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_RSSI_GAIN,
2653 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2655 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2657 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
2658 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2660 bwn_ntab_write_bulk(mac, BWN_NTAB8(0, 8), 4, e->lna1_gain);
2661 bwn_ntab_write_bulk(mac, BWN_NTAB8(1, 8), 4, e->lna1_gain);
2662 bwn_ntab_write_bulk(mac, BWN_NTAB8(0, 16), 4, e->lna2_gain);
2663 bwn_ntab_write_bulk(mac, BWN_NTAB8(1, 16), 4, e->lna2_gain);
2664 bwn_ntab_write_bulk(mac, BWN_NTAB8(0, 32), 10, e->gain_db);
2665 bwn_ntab_write_bulk(mac, BWN_NTAB8(1, 32), 10, e->gain_db);
2666 bwn_ntab_write_bulk(mac, BWN_NTAB8(2, 32), 10, e->gain_bits);
2667 bwn_ntab_write_bulk(mac, BWN_NTAB8(3, 32), 10, e->gain_bits);
2668 bwn_ntab_write_bulk(mac, BWN_NTAB8(0, 0x40), 6, lpf_gain);
2669 bwn_ntab_write_bulk(mac, BWN_NTAB8(1, 0x40), 6, lpf_gain);
2670 bwn_ntab_write_bulk(mac, BWN_NTAB8(2, 0x40), 6, lpf_bits);
2671 bwn_ntab_write_bulk(mac, BWN_NTAB8(3, 0x40), 6, lpf_bits);
2673 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2674 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2676 bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x106), 2,
2679 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2680 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2681 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2682 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2683 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2684 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2686 BWN_PHY_SETMASK(mac, BWN_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2687 BWN_PHY_SETMASK(mac, BWN_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2688 BWN_PHY_SETMASK(mac, BWN_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
2689 BWN_PHY_WRITE(mac, BWN_NPHY_C1_NBCLIPTHRES, e->nbclip);
2690 BWN_PHY_WRITE(mac, BWN_NPHY_C2_NBCLIPTHRES, e->nbclip);
2691 BWN_PHY_SETMASK(mac, BWN_NPHY_C1_CLIPWBTHRES,
2693 BWN_PHY_SETMASK(mac, BWN_NPHY_C2_CLIPWBTHRES,
2695 BWN_PHY_WRITE(mac, BWN_NPHY_CCK_SHIFTB_REF, 0x809C);
2698 static void bwn_nphy_gain_ctl_workarounds_rev1_2(struct bwn_mac *mac)
2700 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
2709 BWN_PHY_SET(mac, BWN_NPHY_C1_CGAINI, BWN_NPHY_C1_CGAINI_CL2DETECT);
2710 BWN_PHY_SET(mac, BWN_NPHY_C2_CGAINI, BWN_NPHY_C2_CGAINI_CL2DETECT);
2713 BWN_PHY_WRITE(mac, BWN_NPHY_C1_NBCLIPTHRES, 0x84);
2714 BWN_PHY_WRITE(mac, BWN_NPHY_C2_NBCLIPTHRES, 0x84);
2716 if (!bwn_is_40mhz(mac)) {
2718 BWN_PHY_WRITE(mac, BWN_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2719 BWN_PHY_WRITE(mac, BWN_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2720 BWN_PHY_WRITE(mac, BWN_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2721 BWN_PHY_WRITE(mac, BWN_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2725 BWN_PHY_SETMASK(mac, BWN_NPHY_C1_CLIPWBTHRES,
2727 BWN_PHY_SETMASK(mac, BWN_NPHY_C2_CLIPWBTHRES,
2730 if (!bwn_is_40mhz(mac)) {
2731 BWN_PHY_SETMASK(mac, BWN_NPHY_C1_CGAINI,
2733 BWN_PHY_SETMASK(mac, BWN_NPHY_C2_CGAINI,
2735 BWN_PHY_SETMASK(mac, BWN_NPHY_C1_CCK_CGAINI,
2737 BWN_PHY_SETMASK(mac, BWN_NPHY_C2_CCK_CGAINI,
2741 BWN_PHY_WRITE(mac, BWN_NPHY_CCK_SHIFTB_REF, 0x809C);
2744 if (bwn_current_band(mac) == BWN_BAND_2G &&
2745 bwn_is_40mhz(mac))
2750 code = bwn_is_40mhz(mac) ? 6 : 7;
2754 BWN_PHY_SETMASK(mac, BWN_NPHY_C1_INITGAIN, ~BWN_NPHY_C1_INITGAIN_HPVGA2,
2756 BWN_PHY_SETMASK(mac, BWN_NPHY_C2_INITGAIN, ~BWN_NPHY_C2_INITGAIN_HPVGA2,
2759 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x1D06);
2762 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2764 bwn_nphy_adjust_lna_gain_table(mac);
2767 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x0808);
2768 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x0);
2769 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1);
2770 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1);
2771 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1);
2773 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x0C08);
2774 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x0);
2775 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1);
2776 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1);
2777 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1);
2779 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x1D06);
2782 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO,
2786 if (mac->mac_phy.rev == 2) {
2788 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR,
2792 BWN_PHY_WRITE(mac,
2798 bwn_nphy_set_rf_sequence(mac, 5, rfseq_events, rfseq_delays, 3);
2799 BWN_PHY_SETMASK(mac, BWN_NPHY_OVER_DGAIN1,
2803 if (bwn_current_band(mac) == BWN_BAND_2G)
2804 BWN_PHY_SETMASK(mac, BWN_PHY_N(0xC5D), 0xFF80, 4);
2808 static void bwn_nphy_gain_ctl_workarounds(struct bwn_mac *mac)
2810 if (mac->mac_phy.rev >= 19)
2811 bwn_nphy_gain_ctl_workarounds_rev19(mac);
2812 else if (mac->mac_phy.rev >= 7)
2813 bwn_nphy_gain_ctl_workarounds_rev7(mac);
2814 else if (mac->mac_phy.rev >= 3)
2815 bwn_nphy_gain_ctl_workarounds_rev3(mac);
2817 bwn_nphy_gain_ctl_workarounds_rev1_2(mac);
2820 static int bwn_nphy_workarounds_rev7plus(struct bwn_mac *mac)
2822 struct bwn_softc *sc = mac->mac_sc;
2823 struct bwn_phy *phy = &mac->mac_phy;
2851 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A0, 0x0125);
2852 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A1, 0x01b3);
2853 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A2, 0x0105);
2854 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B0, 0x016e);
2855 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B1, 0x00cd);
2856 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B2, 0x0020);
2859 BWN_PHY_SET(mac, BWN_NPHY_FINERX2_CGC, 0x10);
2860 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2861 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2862 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2863 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2864 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2865 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2866 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2867 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2868 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2869 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2870 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2871 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2872 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2873 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2874 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2875 BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2879 BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT0, 0x7ff);
2880 BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT1, 0x7ff);
2882 BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT0, 0x1B0);
2883 BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT1, 0x1B0);
2887 BWN_PHY_SETMASK(mac, BWN_NPHY_TXTAILCNT, ~0xFF, 0xa0);
2889 BWN_PHY_SETMASK(mac, BWN_NPHY_TXTAILCNT, ~0xFF, 0x72);
2891 bwn_ntab_write(mac, BWN_NTAB16(8, 0x00), 2);
2892 bwn_ntab_write(mac, BWN_NTAB16(8, 0x10), 2);
2893 tmp32 = bwn_ntab_read(mac, BWN_NTAB32(30, 0));
2895 bwn_ntab_write(mac, BWN_NTAB32(30, 0), tmp32);
2896 bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x15d), 3, ntab7_15e_16e);
2897 bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x16d), 3, ntab7_15e_16e);
2899 bwn_nphy_set_rf_sequence(mac, 1, tx2rx_events, tx2rx_delays,
2901 if (bwn_nphy_ipa(mac))
2902 bwn_nphy_set_rf_sequence(mac, 0, rx2tx_events_ipa,
2905 BWN_PHY_SETMASK(mac, BWN_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2906 BWN_PHY_SETMASK(mac, BWN_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
2909 lpf_ofdm_20mhz[core] = bwn_nphy_read_lpf_ctl(mac, 0x154 + core * 0x10);
2910 lpf_ofdm_40mhz[core] = bwn_nphy_read_lpf_ctl(mac, 0x159 + core * 0x10);
2911 lpf_11b[core] = bwn_nphy_read_lpf_ctl(mac, 0x152 + core * 0x10);
2914 bcap_val = BWN_RF_READ(mac, R2057_RCCAL_BCAP_VAL);
2915 scap_val = BWN_RF_READ(mac, R2057_RCCAL_SCAP_VAL);
2917 if (bwn_nphy_ipa(mac)) {
2918 bool ghz2 = bwn_current_band(mac) == BWN_BAND_2G;
2923 if (phy->rev == 8 && bwn_is_40mhz(mac)) {
2946 if (bwn_current_band(mac) == BWN_BAND_2G) {
3057 bwn_ntab_write(mac, BWN_NTAB16(7, 0x152 + core * 16),
3059 bwn_ntab_write(mac, BWN_NTAB16(7, 0x153 + core * 16),
3061 bwn_ntab_write(mac, BWN_NTAB16(7, 0x154 + core * 16),
3063 bwn_ntab_write(mac, BWN_NTAB16(7, 0x155 + core * 16),
3065 bwn_ntab_write(mac, BWN_NTAB16(7, 0x156 + core * 16),
3067 bwn_ntab_write(mac, BWN_NTAB16(7, 0x157 + core * 16),
3069 bwn_ntab_write(mac, BWN_NTAB16(7, 0x158 + core * 16),
3071 bwn_ntab_write(mac, BWN_NTAB16(7, 0x159 + core * 16),
3076 BWN_PHY_WRITE(mac, 0x32F, 0x3);
3079 bwn_nphy_rf_ctl_override_rev7(mac, 4, 1, 3, false, 0);
3084 BWN_RF_WRITE(mac, 0x5, 0x05);
3085 BWN_RF_WRITE(mac, 0x6, 0x30);
3086 BWN_RF_WRITE(mac, 0x7, 0x00);
3087 BWN_RF_SET(mac, 0x4f, 0x1);
3088 BWN_RF_SET(mac, 0xd4, 0x1);
3097 if (bwn_current_band(mac) == BWN_BAND_2G) {
3100 BWN_RF_WRITE(mac, 0x5F, bias);
3101 BWN_RF_WRITE(mac, 0x64, conv);
3102 BWN_RF_WRITE(mac, 0x66, filt);
3104 BWN_RF_WRITE(mac, 0xE8, bias);
3105 BWN_RF_WRITE(mac, 0xE9, conv);
3106 BWN_RF_WRITE(mac, 0xEB, filt);
3112 if (bwn_nphy_ipa(mac)) {
3113 if (bwn_current_band(mac) == BWN_BAND_2G) {
3118 BWN_RF_WRITE(mac, 0x51,
3121 BWN_RF_WRITE(mac, 0xd6,
3129 BWN_RF_WRITE(mac, 0x64,
3131 BWN_RF_WRITE(mac, 0x5F,
3133 BWN_RF_WRITE(mac, 0x66,
3135 BWN_RF_WRITE(mac, 0x59,
3137 BWN_RF_WRITE(mac, 0x80,
3140 BWN_RF_WRITE(mac, 0x69,
3142 BWN_RF_WRITE(mac, 0xE8,
3144 BWN_RF_WRITE(mac, 0xEB,
3146 BWN_RF_WRITE(mac, 0xDE,
3148 BWN_RF_WRITE(mac, 0x105,
3155 if (!bwn_is_40mhz(mac)) {
3156 BWN_RF_WRITE(mac, 0x5F, 0x14);
3157 BWN_RF_WRITE(mac, 0xE8, 0x12);
3159 BWN_RF_WRITE(mac, 0x5F, 0x16);
3160 BWN_RF_WRITE(mac, 0xE8, 0x16);
3167 BWN_RF_WRITE(mac, o + R2057_IPA2G_CASCONV_CORE0, 0x13);
3168 BWN_RF_WRITE(mac, o + R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 0x21);
3169 BWN_RF_WRITE(mac, o + R2057_IPA2G_BIAS_FILTER_CORE0, 0xff);
3170 BWN_RF_WRITE(mac, o + R2057_PAD2G_IDACS_CORE0, 0x88);
3171 BWN_RF_WRITE(mac, o + R2057_PAD2G_TUNE_PUS_CORE0, 0x23);
3172 BWN_RF_WRITE(mac, o + R2057_IPA2G_IMAIN_CORE0, 0x16);
3173 BWN_RF_WRITE(mac, o + R2057_PAD_BIAS_FILTER_BWS_CORE0, 0x3e);
3174 BWN_RF_WRITE(mac, o + R2057_BACKUP1_CORE0, 0x10);
3179 uint16_t freq = bwn_get_centre_freq(mac);
3182 BWN_RF_WRITE(mac, 0x7D, 0xFF);
3183 BWN_RF_WRITE(mac, 0xFE, 0xFF);
3190 BWN_RF_WRITE(mac, 0x5c, 0x61);
3191 BWN_RF_WRITE(mac, 0x51, 0x70);
3193 BWN_RF_WRITE(mac, 0xe1, 0x61);
3194 BWN_RF_WRITE(mac, 0xd6, 0x70);
3201 bwn_ntab_write(mac, BWN_NTAB16(8, 0x05), 0x20);
3202 bwn_ntab_write(mac, BWN_NTAB16(8, 0x15), 0x20);
3205 BWN_RF_WRITE(mac, 0x1a1, 0x00);
3206 BWN_RF_WRITE(mac, 0x1a2, 0x3f);
3207 BWN_RF_WRITE(mac, 0x1a6, 0x3f);
3209 BWN_RF_WRITE(mac, 0x1a7, 0x00);
3210 BWN_RF_WRITE(mac, 0x1ab, 0x3f);
3211 BWN_RF_WRITE(mac, 0x1ac, 0x3f);
3215 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_C1, 0x4);
3216 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x4);
3217 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_C2, 0x4);
3218 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x4);
3220 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C1, ~0x1);
3221 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x1);
3222 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C2, ~0x1);
3223 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x1);
3224 bwn_ntab_write(mac, BWN_NTAB16(8, 0x05), 0);
3225 bwn_ntab_write(mac, BWN_NTAB16(8, 0x15), 0);
3227 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C1, ~0x4);
3228 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER1, ~0x4);
3229 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C2, ~0x4);
3230 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, ~0x4);
3233 BWN_PHY_WRITE(mac, BWN_NPHY_ENDROP_TLEN, 0x2);
3235 bwn_ntab_write(mac, BWN_NTAB32(16, 0x100), 20);
3236 bwn_ntab_write_bulk(mac, BWN_NTAB8(7, 0x138), 2, ntab7_138_146);
3237 bwn_ntab_write(mac, BWN_NTAB16(7, 0x141), 0x77);
3238 bwn_ntab_write_bulk(mac, BWN_NTAB8(7, 0x133), 3, ntab7_133);
3239 bwn_ntab_write_bulk(mac, BWN_NTAB8(7, 0x146), 2, ntab7_138_146);
3240 bwn_ntab_write(mac, BWN_NTAB16(7, 0x123), 0x77);
3241 bwn_ntab_write(mac, BWN_NTAB16(7, 0x12A), 0x77);
3243 bwn_ntab_read_bulk(mac, BWN_NTAB32(16, 0x02), 1, noise_tbl);
3244 noise_tbl[1] = bwn_is_40mhz(mac) ? 0x14D : 0x18D;
3245 bwn_ntab_write_bulk(mac, BWN_NTAB32(16, 0x02), 2, noise_tbl);
3247 bwn_ntab_read_bulk(mac, BWN_NTAB32(16, 0x7E), 1, noise_tbl);
3248 noise_tbl[1] = bwn_is_40mhz(mac) ? 0x14D : 0x18D;
3249 bwn_ntab_write_bulk(mac, BWN_NTAB32(16, 0x7E), 2, noise_tbl);
3251 bwn_nphy_gain_ctl_workarounds(mac);
3254 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x08), 4,
3256 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x18), 4,
3258 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x0C), 4,
3260 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1C), 4,
3267 static int bwn_nphy_workarounds_rev3plus(struct bwn_mac *mac)
3269 struct bwn_softc *sc = mac->mac_sc;
3270 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
3304 BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT0, 0x1f8);
3305 BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT1, 0x1f8);
3307 tmp32 = bwn_ntab_read(mac, BWN_NTAB32(30, 0));
3309 bwn_ntab_write(mac, BWN_NTAB32(30, 0), tmp32);
3311 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A0, 0x0125);
3312 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A1, 0x01B3);
3313 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A2, 0x0105);
3314 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B0, 0x016E);
3315 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B1, 0x00CD);
3316 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B2, 0x0020);
3318 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
3319 BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
3322 bwn_nphy_set_rf_sequence(mac, 1, tx2rx_events, tx2rx_delays,
3326 if (bwn_nphy_ipa(mac))
3327 bwn_nphy_set_rf_sequence(mac, 0, rx2tx_events_ipa,
3331 if (bwn_nphy_ipa(mac)) {
3336 bwn_nphy_set_rf_sequence(mac, 0, rx2tx_events, rx2tx_delays,
3340 tmp16 = (bwn_current_band(mac) == BWN_BAND_2G) ?
3342 BWN_PHY_WRITE(mac, BWN_NPHY_ENDROP_TLEN, tmp16);
3344 BWN_PHY_SETMASK(mac, BWN_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
3346 if (!bwn_is_40mhz(mac)) {
3347 bwn_ntab_write(mac, BWN_NTAB32(16, 3), 0x18D);
3348 bwn_ntab_write(mac, BWN_NTAB32(16, 127), 0x18D);
3350 bwn_ntab_write(mac, BWN_NTAB32(16, 3), 0x14D);
3351 bwn_ntab_write(mac, BWN_NTAB32(16, 127), 0x14D);
3354 bwn_nphy_gain_ctl_workarounds(mac);
3356 bwn_ntab_write(mac, BWN_NTAB16(8, 0), 2);
3357 bwn_ntab_write(mac, BWN_NTAB16(8, 16), 2);
3359 if (bwn_current_band(mac) == BWN_BAND_2G)
3367 BWN_ERRPRINTF(mac->mac_sc, "Error reading PDet range %s from "
3377 if (!(mac->mac_phy.rev >= 4 &&
3378 bwn_current_band(mac) == BWN_BAND_2G))
3383 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x08), 4, vmid);
3384 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x18), 4, vmid);
3385 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x0c), 4, gain);
3386 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1c), 4, gain);
3389 if (mac->mac_phy.rev >= 6) {
3390 if (bwn_current_band(mac) == BWN_BAND_2G)
3395 } else if (mac->mac_phy.rev == 5) {
3399 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x08), 4, vmid);
3400 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x18), 4, vmid);
3401 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x0c), 4, gain);
3402 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1c), 4, gain);
3406 if (bwn_current_band(mac) != BWN_BAND_2G) {
3427 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x08), 4, vmid);
3428 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x0c), 4, gain);
3430 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x18), 4, vmid);
3431 bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1c), 4, gain);
3435 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
3436 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
3437 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
3438 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
3439 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
3440 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
3441 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
3442 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
3443 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
3444 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
3445 BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
3446 BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
3451 bwn_current_band(mac) == BWN_BAND_5G) ||
3453 bwn_current_band(mac) == BWN_BAND_2G))
3457 bwn_ntab_write(mac, BWN_NTAB32(30, 1), tmp32);
3458 bwn_ntab_write(mac, BWN_NTAB32(30, 2), tmp32);
3459 bwn_ntab_write(mac, BWN_NTAB32(30, 3), tmp32);
3461 if (mac->mac_phy.rev == 4 &&
3462 bwn_current_band(mac) == BWN_BAND_5G) {
3463 BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_GMBB_IDAC,
3465 BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_GMBB_IDAC,
3470 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
3471 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
3472 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341);
3473 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
3474 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
3475 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
3476 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
3477 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
3478 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
3479 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
3480 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
3481 BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
3483 if (mac->mac_phy.rev >= 6 && sc->sc_board_info.board_flags2 & BHND_BFL2_SINGLEANT_CCK)
3489 static int bwn_nphy_workarounds_rev1_2(struct bwn_mac *mac)
3491 struct bwn_softc *sc = mac->mac_sc;
3492 struct bwn_phy *phy = &mac->mac_phy;
3507 if (bwn_current_band(mac) == BWN_BAND_5G &&
3509 BWN_RF_MASK(mac, B2055_C1_TX_RF_SPARE, ~0x8);
3510 BWN_RF_MASK(mac, B2055_C2_TX_RF_SPARE, ~0x8);
3512 BWN_RF_SET(mac, B2055_C1_TX_RF_SPARE, 0x8);
3513 BWN_RF_SET(mac, B2055_C2_TX_RF_SPARE, 0x8);
3516 bwn_ntab_write(mac, BWN_NTAB16(8, 0x00), 0x000A);
3517 bwn_ntab_write(mac, BWN_NTAB16(8, 0x10), 0x000A);
3518 if (mac->mac_phy.rev < 3) {
3519 bwn_ntab_write(mac, BWN_NTAB16(8, 0x02), 0xCDAA);
3520 bwn_ntab_write(mac, BWN_NTAB16(8, 0x12), 0xCDAA);
3523 if (mac->mac_phy.rev < 2) {
3524 bwn_ntab_write(mac, BWN_NTAB16(8, 0x08), 0x0000);
3525 bwn_ntab_write(mac, BWN_NTAB16(8, 0x18), 0x0000);
3526 bwn_ntab_write(mac, BWN_NTAB16(8, 0x07), 0x7AAB);
3527 bwn_ntab_write(mac, BWN_NTAB16(8, 0x17), 0x7AAB);
3528 bwn_ntab_write(mac, BWN_NTAB16(8, 0x06), 0x0800);
3529 bwn_ntab_write(mac, BWN_NTAB16(8, 0x16), 0x0800);
3532 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
3533 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
3534 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
3535 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
3537 bwn_nphy_set_rf_sequence(mac, 0, events1, delays1, 7);
3538 bwn_nphy_set_rf_sequence(mac, 1, events2, delays2, 7);
3540 bwn_nphy_gain_ctl_workarounds(mac);
3542 if (mac->mac_phy.rev < 2) {
3543 if (BWN_PHY_READ(mac, BWN_NPHY_RXCTL) & 0x2)
3544 bwn_hf_write(mac, bwn_hf_read(mac) |
3546 } else if (mac->mac_phy.rev == 2) {
3547 BWN_PHY_WRITE(mac, BWN_NPHY_CRSCHECK2, 0);
3548 BWN_PHY_WRITE(mac, BWN_NPHY_CRSCHECK3, 0);
3551 if (mac->mac_phy.rev < 2)
3552 BWN_PHY_MASK(mac, BWN_NPHY_SCRAM_SIGCTL,
3556 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A0, 0x125);
3557 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A1, 0x1B3);
3558 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A2, 0x105);
3559 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B0, 0x16E);
3560 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B1, 0xCD);
3561 BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B2, 0x20);
3563 if (mac->mac_phy.rev < 3) {
3564 BWN_PHY_MASK(mac, BWN_NPHY_PIL_DW1,
3566 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_20CO_S2B1, 0xB5);
3567 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_20CO_S2B2, 0xA4);
3568 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_20CO_S2B3, 0x00);
3571 if (mac->mac_phy.rev == 2)
3572 BWN_PHY_SET(mac, BWN_NPHY_FINERX2_CGC,
3579 static int bwn_nphy_workarounds(struct bwn_mac *mac)
3581 struct bwn_phy *phy = &mac->mac_phy;
3585 if (bwn_current_band(mac) == BWN_BAND_5G)
3586 bwn_nphy_classifier(mac, 1, 0);
3588 bwn_nphy_classifier(mac, 1, 1);
3591 bwn_nphy_stay_in_carrier_search(mac, 1);
3593 BWN_PHY_SET(mac, BWN_NPHY_IQFLIP,
3597 if (mac->mac_phy.rev >= 7)
3598 error = bwn_nphy_workarounds_rev7plus(mac);
3599 else if (mac->mac_phy.rev >= 3)
3600 error = bwn_nphy_workarounds_rev3plus(mac);
3602 error = bwn_nphy_workarounds_rev1_2(mac);
3608 bwn_nphy_stay_in_carrier_search(mac, 0);
3621 static int bwn_nphy_tx_tone(struct bwn_mac *mac, uint32_t freq, uint16_t max_val,
3624 uint16_t samp = bwn_nphy_gen_load_samples(mac, freq, max_val, dac_test);
3627 bwn_nphy_run_samples(mac, samp, 0xFFFF, 0, iqmode, dac_test,
3633 static void bwn_nphy_update_txrx_chain(struct bwn_mac *mac)
3635 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
3648 BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA,
3653 BWN_PHY_SET(mac, BWN_NPHY_RFSEQMODE,
3656 BWN_PHY_MASK(mac, BWN_NPHY_RFSEQMODE,
3661 static void bwn_nphy_stop_playback(struct bwn_mac *mac)
3663 struct bwn_phy *phy = &mac->mac_phy;
3664 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
3668 bwn_nphy_stay_in_carrier_search(mac, 1);
3670 tmp = BWN_PHY_READ(mac, BWN_NPHY_SAMP_STAT);
3672 BWN_PHY_SET(mac, BWN_NPHY_SAMP_CMD, BWN_NPHY_SAMP_CMD_STOP);
3674 BWN_PHY_MASK(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
3676 BWN_PHY_MASK(mac, BWN_NPHY_SAMP_CMD, ~0x0004);
3680 bwn_ntab_write(mac, BWN_NTAB16(15, 87), tmp);
3686 bwn_nphy_rf_ctl_override_rev19(mac, 0x80, 0, 0, true,
3689 bwn_nphy_rf_ctl_override_rev7(mac, 0x80, 0, 0, true, 1);
3694 bwn_nphy_stay_in_carrier_search(mac, 0);
3698 static void bwn_nphy_iq_cal_gain_params(struct bwn_mac *mac, uint16_t core,
3702 struct bwn_phy *phy = &mac->mac_phy;
3706 if (mac->mac_phy.rev >= 3) {
3725 indx = (bwn_current_band(mac) == BWN_BAND_5G) ?
3747 static void bwn_nphy_tx_power_ctrl(struct bwn_mac *mac, bool enable)
3749 struct bwn_phy *phy = &mac->mac_phy;
3750 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
3753 bwn_band_t band = bwn_current_band(mac);
3756 bwn_nphy_stay_in_carrier_search(mac, 1);
3760 if (mac->mac_phy.rev >= 3 &&
3761 (BWN_PHY_READ(mac, BWN_NPHY_TXPCTL_CMD) &
3766 nphy->tx_pwr_idx[0] = BWN_PHY_READ(mac,
3768 nphy->tx_pwr_idx[1] = BWN_PHY_READ(mac,
3772 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x6840);
3774 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0);
3776 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x6C40);
3778 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0);
3781 if (mac->mac_phy.rev >= 3)
3783 BWN_PHY_MASK(mac, BWN_NPHY_TXPCTL_CMD, ~tmp);
3785 if (mac->mac_phy.rev >= 3) {
3786 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x0100);
3787 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x0100);
3789 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x4000);
3792 if (mac->mac_phy.rev == 2)
3793 BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3,
3795 else if (mac->mac_phy.rev < 2)
3796 BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3,
3799 if (mac->mac_phy.rev < 2 && bwn_is_40mhz(mac))
3800 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_TSSI_RESET_PSM_WORKAROUN);
3802 bwn_ntab_write_bulk(mac, BWN_NTAB16(26, 64), 84,
3804 bwn_ntab_write_bulk(mac, BWN_NTAB16(27, 64), 84,
3811 if (mac->mac_phy.rev >= 3) {
3816 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD, ~(bmask), val);
3822 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD,
3825 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_INIT,
3829 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD,
3833 BWN_PHY_SETMASK(mac,
3840 if (mac->mac_phy.rev >= 3) {
3844 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD,
3847 if (mac->mac_phy.rev > 1)
3848 BWN_PHY_SETMASK(mac,
3858 if (mac->mac_phy.rev >= 3) {
3859 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER1, ~0x100);
3860 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, ~0x100);
3862 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, ~0x4000);
3865 if (mac->mac_phy.rev == 2)
3866 BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
3867 else if (mac->mac_phy.rev < 2)
3868 BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3, ~0xFF, 0x40);
3870 if (mac->mac_phy.rev < 2 && bwn_is_40mhz(mac))
3871 bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_TSSI_RESET_PSM_WORKAROUN);
3873 if (bwn_nphy_ipa(mac)) {
3874 BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN0, ~0x4);
3875 BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN1, ~0x4);
3880 bwn_nphy_stay_in_carrier_search(mac, 0);
3884 static int bwn_nphy_tx_power_fix(struct bwn_mac *mac)
3886 struct bwn_softc *sc = mac->mac_sc;
3887 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
3891 uint16_t freq = bwn_get_centre_freq(mac);
3896 bwn_nphy_stay_in_carrier_search(mac, 1);
3899 if (mac->mac_phy.rev >= 7) {
3901 } else if (mac->mac_phy.rev >= 3) {
3923 if (bwn_current_band(mac) == BWN_BAND_2G) {
3942 if (mac->mac_phy.rev < 7 &&
3954 const uint32_t *table = bwn_nphy_get_tx_gain_table(mac);
3960 if (mac->mac_phy.rev >= 3)
3965 if (mac->mac_phy.rev >= 7)
3971 if (mac->mac_phy.rev >= 3) {
3973 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x0100);
3975 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x0100);
3977 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x4000);
3981 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_DACGAIN1, dac_gain);
3983 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_DACGAIN2, dac_gain);
3985 bwn_ntab_write(mac, BWN_NTAB16(0x7, 0x110 + i), radio_gain);
3987 tmp = bwn_ntab_read(mac, BWN_NTAB16(0xF, 0x57));
3992 bwn_ntab_write(mac, BWN_NTAB16(0xF, 0x57), tmp);
3994 if (bwn_nphy_ipa(mac)) {
3998 tmp32 = bwn_ntab_read(mac, BWN_NTAB32(26 + i,
4000 BWN_PHY_SETMASK(mac, reg, 0xE00F, (uint32_t) tmp32 << 4);
4001 BWN_PHY_SET(mac, reg, 0x4);
4005 BWN_PHY_MASK(mac, BWN_NPHY_BPHY_CTL2, ~BWN_NPHY_BPHY_CTL2_LUT);
4008 bwn_nphy_stay_in_carrier_search(mac, 0);
4013 static void bwn_nphy_ipa_internal_tssi_setup(struct bwn_mac *mac)
4015 struct bwn_phy *phy = &mac->mac_phy;
4025 if (bwn_current_band(mac) == BWN_BAND_2G) {
4026 BWN_RF_WRITE(mac, r + 0x5, 0x5);
4027 BWN_RF_WRITE(mac, r + 0x9, 0xE);
4029 BWN_RF_WRITE(mac, r + 0xA, 0);
4031 BWN_RF_WRITE(mac, r + 0xB, 1);
4033 BWN_RF_WRITE(mac, r + 0xB, 0x31);
4035 BWN_RF_WRITE(mac, r + 0x5, 0x9);
4036 BWN_RF_WRITE(mac, r + 0x9, 0xC);
4037 BWN_RF_WRITE(mac, r + 0xB, 0x0);
4039 BWN_RF_WRITE(mac, r + 0xA, 1);
4041 BWN_RF_WRITE(mac, r + 0xA, 0x31);
4043 BWN_RF_WRITE(mac, r + 0x6, 0);
4044 BWN_RF_WRITE(mac, r + 0x7, 0);
4045 BWN_RF_WRITE(mac, r + 0x8, 3);
4046 BWN_RF_WRITE(mac, r + 0xC, 0);
4049 if (bwn_current_band(mac) == BWN_BAND_2G)
4050 BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR31, 0x128);
4052 BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR31, 0x80);
4053 BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR30, 0);
4054 BWN_RF_WRITE(mac, B2056_SYN_GPIO_MASTER1, 0x29);
4059 BWN_RF_WRITE(mac, r | B2056_TX_IQCAL_VCM_HG, 0);
4060 BWN_RF_WRITE(mac, r | B2056_TX_IQCAL_IDAC, 0);
4061 BWN_RF_WRITE(mac, r | B2056_TX_TSSI_VCM, 3);
4062 BWN_RF_WRITE(mac, r | B2056_TX_TX_AMP_DET, 0);
4063 BWN_RF_WRITE(mac, r | B2056_TX_TSSI_MISC1, 8);
4064 BWN_RF_WRITE(mac, r | B2056_TX_TSSI_MISC2, 0);
4065 BWN_RF_WRITE(mac, r | B2056_TX_TSSI_MISC3, 0);
4066 if (bwn_current_band(mac) == BWN_BAND_2G) {
4067 BWN_RF_WRITE(mac, r | B2056_TX_TX_SSI_MASTER,
4070 BWN_RF_WRITE(mac, r | B2056_TX_TSSIA,
4073 BWN_RF_WRITE(mac, r | B2056_TX_TSSIG,
4076 BWN_RF_WRITE(mac, r | B2056_TX_TSSIG,
4078 BWN_RF_WRITE(mac, r | B2056_TX_TX_SSI_MUX,
4081 BWN_RF_WRITE(mac, r | B2056_TX_TX_SSI_MASTER,
4083 BWN_RF_WRITE(mac, r | B2056_TX_TSSIA, 0x31);
4084 BWN_RF_WRITE(mac, r | B2056_TX_TSSIG, 0x0);
4085 BWN_RF_WRITE(mac, r | B2056_TX_TX_SSI_MUX,
4097 static void bwn_nphy_tx_power_ctl_idle_tssi(struct bwn_mac *mac)
4099 struct bwn_phy *phy = &mac->mac_phy;
4100 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
4105 if (bwn_is_chan_passive(mac))
4108 if (bwn_nphy_ipa(mac))
4109 bwn_nphy_ipa_internal_tssi_setup(mac);
4112 bwn_nphy_rf_ctl_override_rev19(mac, 0x1000, 0, 3, false, 0);
4114 bwn_nphy_rf_ctl_override_rev7(mac, 0x1000, 0, 3, false, 0);
4116 bwn_nphy_rf_ctl_override(mac, 0x2000, 0, 3, false);
4118 bwn_nphy_stop_playback(mac);
4119 bwn_nphy_tx_tone(mac, 4000, 0, false, false, false);
4121 tmp = bwn_nphy_poll_rssi(mac, N_RSSI_TSSI_2G, rssi, 1);
4122 bwn_nphy_stop_playback(mac);
4124 bwn_nphy_rssi_select(mac, 0, N_RSSI_W1);
4127 bwn_nphy_rf_ctl_override_rev19(mac, 0x1000, 0, 3, true, 0);
4129 bwn_nphy_rf_ctl_override_rev7(mac, 0x1000, 0, 3, true, 0);
4131 bwn_nphy_rf_ctl_override(mac, 0x2000, 0, 3, true);
4148 static void bwn_nphy_tx_prepare_adjusted_power_table(struct bwn_mac *mac)
4150 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
4176 if (bwn_is_40mhz(mac) && mac->mac_phy.rev >= 5) {
4180 idx = bwn_is_40mhz(mac) ? 52 : 4;
4184 idx = bwn_is_40mhz(mac) ? 76 : 28;
4187 idx = bwn_is_40mhz(mac) ? 84 : 36;
4190 idx = bwn_is_40mhz(mac) ? 92 : 44;
4209 static void bwn_nphy_tx_power_ctl_setup(struct bwn_mac *mac)
4211 struct bwn_softc *sc = mac->mac_sc;
4212 struct bwn_phy *phy = &mac->mac_phy;
4213 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
4224 uint16_t freq = bwn_get_centre_freq(mac);
4231 if (bwn_nphy_get_core_power_info(mac, n,
4233 BWN_ERRPRINTF(mac->mac_sc,
4241 BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0, 0x200000);
4242 BWN_READ_4(mac, BWN_MACCTL);
4247 bwn_nphy_stay_in_carrier_search(mac, true);
4249 BWN_PHY_SET(mac, BWN_NPHY_TSSIMODE, BWN_NPHY_TSSIMODE_EN);
4250 if (mac->mac_phy.rev >= 3)
4251 BWN_PHY_MASK(mac, BWN_NPHY_TXPCTL_CMD,
4254 BWN_PHY_SET(mac, BWN_NPHY_TXPCTL_CMD,
4258 BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0x200000, 0);
4272 if (bwn_current_band(mac) == BWN_BAND_2G) {
4314 ppr_max = bwn_ppr_get_max(mac, &nphy->tx_pwr_max_ppr);
4320 if (mac->mac_phy.rev >= 3) {
4322 BWN_PHY_SET(mac, BWN_NPHY_TXPCTL_ITSSI, 0x4000);
4323 if (mac->mac_phy.rev >= 7) {
4326 if (bwn_nphy_ipa(mac))
4327 BWN_RF_WRITE(mac, r + 0x9, (bwn_current_band(mac) == BWN_BAND_2G) ? 0xE : 0xC);
4330 if (bwn_nphy_ipa(mac)) {
4331 tmp = (bwn_current_band(mac) == BWN_BAND_5G) ? 0xC : 0xE;
4332 BWN_RF_WRITE(mac,
4334 BWN_RF_WRITE(mac,
4337 BWN_RF_WRITE(mac,
4339 BWN_RF_WRITE(mac,
4346 BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0, 0x200000);
4347 BWN_READ_4(mac, BWN_MACCTL);
4354 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD,
4356 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_INIT,
4359 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD,
4361 if (mac->mac_phy.rev > 1)
4362 BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_INIT,
4367 BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0x200000, 0);
4369 BWN_PHY_WRITE(mac, BWN_NPHY_TXPCTL_N,
4372 BWN_PHY_WRITE(mac, BWN_NPHY_TXPCTL_ITSSI,
4376 BWN_PHY_WRITE(mac, BWN_NPHY_TXPCTL_TPWR,
4385 if (mac->mac_phy.rev < 3 && (i <= (31 - idle[c] + 1)))
4389 bwn_ntab_write_bulk(mac, BWN_NTAB32(26 + c, 0), 64, regval);
4392 bwn_nphy_tx_prepare_adjusted_power_table(mac);
4393 bwn_ntab_write_bulk(mac, BWN_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
4394 bwn_ntab_write_bulk(mac, BWN_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
4397 bwn_nphy_stay_in_carrier_search(mac, false);
4400 static void bwn_nphy_tx_gain_table_upload(struct bwn_mac *mac)
4402 struct bwn_phy *phy = &mac->mac_phy;
4410 table = bwn_nphy_get_tx_gain_table(mac);
4414 bwn_ntab_write_bulk(mac, BWN_NTAB32(26, 192), 128, table);
4415 bwn_ntab_write_bulk(mac, BWN_NTAB32(27, 192), 128, table);
4427 rf_pwr_offset_table = bwn_ntab_get_rf_pwr_offset_table(mac);
4441 if (bwn_current_band(mac) == BWN_BAND_2G)
4447 if (bwn_current_band(mac) == BWN_BAND_2G)
4453 bwn_ntab_write(mac, BWN_NTAB32(26, 576 + i), rfpwr_offset);
4454 bwn_ntab_write(mac, BWN_NTAB32(27, 576 + i), rfpwr_offset);
4459 static void bwn_nphy_pa_override(struct bwn_mac *mac, bool enable)
4461 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
4466 nphy->rfctrl_intc1_save = BWN_PHY_READ(mac,
4468 nphy->rfctrl_intc2_save = BWN_PHY_READ(mac,
4470 band = bwn_current_band(mac);
4471 if (mac->mac_phy.rev >= 7) {
4473 } else if (mac->mac_phy.rev >= 3) {
4484 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, tmp);
4485 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, tmp);
4487 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1,
4489 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2,
4498 static void bwn_nphy_tx_lpf_bw(struct bwn_mac *mac)
4502 if (mac->mac_phy.rev < 3 || mac->mac_phy.rev >= 7)
4505 if (bwn_nphy_ipa(mac))
4506 tmp = bwn_is_40mhz(mac) ? 5 : 4;
4508 tmp = bwn_is_40mhz(mac) ? 3 : 1;
4509 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B32S2,
4512 if (bwn_nphy_ipa(mac)) {
4513 tmp = bwn_is_40mhz(mac) ? 4 : 1;
4514 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S2,
4520 static void bwn_nphy_rx_iq_est(struct bwn_mac *mac, struct bwn_nphy_iq_est *est,
4526 BWN_PHY_WRITE(mac, BWN_NPHY_IQEST_SAMCNT, samps);
4527 BWN_PHY_SETMASK(mac, BWN_NPHY_IQEST_WT, ~BWN_NPHY_IQEST_WT_VAL, time);
4529 BWN_PHY_SET(mac, BWN_NPHY_IQEST_CMD, BWN_NPHY_IQEST_CMD_MODE);
4531 BWN_PHY_MASK(mac, BWN_NPHY_IQEST_CMD, ~BWN_NPHY_IQEST_CMD_MODE);
4533 BWN_PHY_SET(mac, BWN_NPHY_IQEST_CMD, BWN_NPHY_IQEST_CMD_START);
4536 tmp = BWN_PHY_READ(mac, BWN_NPHY_IQEST_CMD);
4538 est->i0_pwr = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_IPACC_HI0) << 16) |
4539 BWN_PHY_READ(mac, BWN_NPHY_IQEST_IPACC_LO0);
4540 est->q0_pwr = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_QPACC_HI0) << 16) |
4541 BWN_PHY_READ(mac, BWN_NPHY_IQEST_QPACC_LO0);
4542 est->iq0_prod = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_IQACC_HI0) << 16) |
4543 BWN_PHY_READ(mac, BWN_NPHY_IQEST_IQACC_LO0);
4545 est->i1_pwr = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_IPACC_HI1) << 16) |
4546 BWN_PHY_READ(mac, BWN_NPHY_IQEST_IPACC_LO1);
4547 est->q1_pwr = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_QPACC_HI1) << 16) |
4548 BWN_PHY_READ(mac, BWN_NPHY_IQEST_QPACC_LO1);
4549 est->iq1_prod = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_IQACC_HI1) << 16) |
4550 BWN_PHY_READ(mac, BWN_NPHY_IQEST_IQACC_LO1);
4559 static void bwn_nphy_rx_iq_coeffs(struct bwn_mac *mac, bool write,
4563 BWN_PHY_WRITE(mac, BWN_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
4564 BWN_PHY_WRITE(mac, BWN_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
4565 BWN_PHY_WRITE(mac, BWN_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
4566 BWN_PHY_WRITE(mac, BWN_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
4568 pcomp->a0 = BWN_PHY_READ(mac, BWN_NPHY_C1_RXIQ_COMPA0);
4569 pcomp->b0 = BWN_PHY_READ(mac, BWN_NPHY_C1_RXIQ_COMPB0);
4570 pcomp->a1 = BWN_PHY_READ(mac, BWN_NPHY_C2_RXIQ_COMPA1);
4571 pcomp->b1 = BWN_PHY_READ(mac, BWN_NPHY_C2_RXIQ_COMPB1);
4578 static void bwn_nphy_rx_cal_phy_cleanup(struct bwn_mac *mac, uint8_t core)
4580 uint16_t *regs = mac->mac_phy.phy_n->tx_rx_cal_phy_saveregs;
4582 BWN_PHY_WRITE(mac, BWN_NPHY_RFSEQCA, regs[0]);
4584 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, regs[1]);
4585 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, regs[2]);
4587 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, regs[1]);
4588 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, regs[2]);
4590 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, regs[3]);
4591 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, regs[4]);
4592 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_RSSIO1, regs[5]);
4593 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_RSSIO2, regs[6]);
4594 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S1, regs[7]);
4595 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_OVER, regs[8]);
4596 BWN_PHY_WRITE(mac, BWN_NPHY_PAPD_EN0, regs[9]);
4597 BWN_PHY_WRITE(mac, BWN_NPHY_PAPD_EN1, regs[10]);
4601 static void bwn_nphy_rx_cal_phy_setup(struct bwn_mac *mac, uint8_t core)
4604 uint16_t *regs = mac->mac_phy.phy_n->tx_rx_cal_phy_saveregs;
4606 regs[0] = BWN_PHY_READ(mac, BWN_NPHY_RFSEQCA);
4608 regs[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C1);
4609 regs[2] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER1);
4611 regs[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C2);
4612 regs[2] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER);
4614 regs[3] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1);
4615 regs[4] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2);
4616 regs[5] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_RSSIO1);
4617 regs[6] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_RSSIO2);
4618 regs[7] = BWN_PHY_READ(mac, BWN_NPHY_TXF_40CO_B1S1);
4619 regs[8] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_OVER);
4620 regs[9] = BWN_PHY_READ(mac, BWN_NPHY_PAPD_EN0);
4621 regs[10] = BWN_PHY_READ(mac, BWN_NPHY_PAPD_EN1);
4623 BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN0, ~0x0001);
4624 BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN1, ~0x0001);
4626 BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA,
4629 BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_TXEN,
4631 BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_RXEN,
4633 BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_TXDIS,
4637 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C1, ~0x0007);
4638 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x0007);
4640 BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C2, ~0x0007);
4641 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x0007);
4644 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_PA, 0, 3);
4645 bwn_nphy_rf_ctl_override(mac, 8, 0, 3, false);
4646 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RX2TX);
4655 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, rxval,
4657 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, txval,
4663 static void bwn_nphy_calc_rx_iq_comp(struct bwn_mac *mac, uint8_t mask)
4681 bwn_nphy_rx_iq_coeffs(mac, false, &old);
4682 bwn_nphy_rx_iq_coeffs(mac, true, &new);
4683 bwn_nphy_rx_iq_est(mac, &est, 0x4000, 32, false);
4733 b = bwn_sqrt(mac, b / tmp - a * a) - (1 << 10);
4736 if (mac->mac_phy.rev >= 3) {
4744 if (mac->mac_phy.rev >= 3) {
4757 bwn_nphy_rx_iq_coeffs(mac, true, &new);
4761 static void bwn_nphy_tx_iq_workaround(struct bwn_mac *mac)
4764 bwn_ntab_read_bulk(mac, BWN_NTAB16(0xF, 0x50), 4, array);
4766 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXIQW0, array[0]);
4767 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXIQW1, array[1]);
4768 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXIQW2, array[2]);
4769 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXIQW3, array[3]);
4773 static void bwn_nphy_spur_workaround(struct bwn_mac *mac)
4775 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
4777 uint8_t channel = bwn_get_chan(mac);
4781 if (mac->mac_phy.rev < 3) {
4782 BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n",
4784 mac->mac_phy.rev);
4788 bwn_nphy_stay_in_carrier_search(mac, 1);
4792 if (channel == 11 && bwn_is_40mhz(mac))
4832 bwn_nphy_stay_in_carrier_search(mac, 0);
4836 static void bwn_nphy_tx_pwr_ctrl_coef_setup(struct bwn_mac *mac)
4838 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
4846 bwn_nphy_stay_in_carrier_search(mac, true);
4848 bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 80), 7, buffer);
4853 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR,
4856 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATAHI,
4858 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO,
4867 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR,
4870 if (mac->mac_phy.rev >= 3) {
4877 if (mac->mac_phy.rev < 3) {
4883 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATAHI,
4885 BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO,
4890 if (mac->mac_phy.rev >= 3) {
4891 bwn_shm_write_2(mac, BWN_SHARED,
4893 bwn_shm_write_2(mac, BWN_SHARED,
4898 bwn_nphy_stay_in_carrier_search(mac, false);
4905 static void bwn_nphy_restore_rssi_cal(struct bwn_mac *mac)
4907 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
4912 if (bwn_current_band(mac) == BWN_BAND_2G) {
4924 if (mac->mac_phy.rev >= 19) {
4926 } else if (mac->mac_phy.rev >= 7) {
4927 BWN_RF_SETMASK(mac, R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK,
4929 BWN_RF_SETMASK(mac, R2057_NB_MASTER_CORE1, ~R2057_VCM_MASK,
4932 BWN_RF_SETMASK(mac, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
4934 BWN_RF_SETMASK(mac, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
4938 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
4939 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
4940 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
4941 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
4943 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
4944 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
4945 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
4946 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
4948 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
4949 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
4950 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
4951 BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
4954 static void bwn_nphy_tx_cal_radio_setup_rev19(struct bwn_mac *mac)
4959 static void bwn_nphy_tx_cal_radio_setup_rev7(struct bwn_mac *mac)
4961 struct bwn_phy *phy = &mac->mac_phy;
4962 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
4971 save[off + 0] = BWN_RF_READ(mac, r + R2057_TX0_TX_SSI_MASTER);
4972 save[off + 1] = BWN_RF_READ(mac, r + R2057_TX0_IQCAL_VCM_HG);
4973 save[off + 2] = BWN_RF_READ(mac, r + R2057_TX0_IQCAL_IDAC);
4974 save[off + 3] = BWN_RF_READ(mac, r + R2057_TX0_TSSI_VCM);
4976 save[off + 5] = BWN_RF_READ(mac, r + R2057_TX0_TX_SSI_MUX);
4978 save[off + 6] = BWN_RF_READ(mac, r + R2057_TX0_TSSIA);
4979 save[off + 7] = BWN_RF_READ(mac, r + R2057_TX0_TSSIG);
4980 save[off + 8] = BWN_RF_READ(mac, r + R2057_TX0_TSSI_MISC1);
4982 if (bwn_current_band(mac) == BWN_BAND_5G) {
4983 BWN_RF_WRITE(mac, r + R2057_TX0_TX_SSI_MASTER, 0xA);
4984 BWN_RF_WRITE(mac, r + R2057_TX0_IQCAL_VCM_HG, 0x43);
4985 BWN_RF_WRITE(mac, r + R2057_TX0_IQCAL_IDAC, 0x55);
4986 BWN_RF_WRITE(mac, r + R2057_TX0_TSSI_VCM, 0);
4987 BWN_RF_WRITE(mac, r + R2057_TX0_TSSIG, 0);
4989 BWN_RF_WRITE(mac, r + R2057_TX0_TX_SSI_MUX, 0x4);
4991 BWN_RF_WRITE(mac, r + R2057_TX0_TSSIA, tmp);
4993 BWN_RF_WRITE(mac, r + R2057_TX0_TSSI_MISC1, 0x00);
4995 BWN_RF_WRITE(mac, r + R2057_TX0_TX_SSI_MASTER, 0x6);
4996 BWN_RF_WRITE(mac, r + R2057_TX0_IQCAL_VCM_HG, 0x43);
4997 BWN_RF_WRITE(mac, r + R2057_TX0_IQCAL_IDAC, 0x55);
4998 BWN_RF_WRITE(mac, r + R2057_TX0_TSSI_VCM, 0);
5001 BWN_RF_WRITE(mac, r + R2057_TX0_TSSIA, 0);
5003 BWN_RF_WRITE(mac, r + R2057_TX0_TX_SSI_MUX, 0x6);
5005 BWN_RF_WRITE(mac, r + R2057_TX0_TSSIG, tmp);
5007 BWN_RF_WRITE(mac, r + R2057_TX0_TSSI_MISC1, 0);
5013 static void bwn_nphy_tx_cal_radio_setup(struct bwn_mac *mac)
5015 struct bwn_phy *phy = &mac->mac_phy;
5016 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5022 bwn_nphy_tx_cal_radio_setup_rev19(mac);
5024 bwn_nphy_tx_cal_radio_setup_rev7(mac);
5030 save[offset + 0] = BWN_RF_READ(mac, B2055_CAL_RVARCTL);
5031 save[offset + 1] = BWN_RF_READ(mac, B2055_CAL_LPOCTL);
5032 save[offset + 2] = BWN_RF_READ(mac, B2055_CAL_TS);
5033 save[offset + 3] = BWN_RF_READ(mac, B2055_CAL_RCCALRTS);
5034 save[offset + 4] = BWN_RF_READ(mac, B2055_CAL_RCALRTS);
5035 save[offset + 5] = BWN_RF_READ(mac, B2055_PADDRV);
5036 save[offset + 6] = BWN_RF_READ(mac, B2055_XOCTL1);
5037 save[offset + 7] = BWN_RF_READ(mac, B2055_XOCTL2);
5038 save[offset + 8] = BWN_RF_READ(mac, B2055_XOREGUL);
5039 save[offset + 9] = BWN_RF_READ(mac, B2055_XOMISC);
5040 save[offset + 10] = BWN_RF_READ(mac, B2055_PLL_LFC1);
5042 if (bwn_current_band(mac) == BWN_BAND_5G) {
5043 BWN_RF_WRITE(mac, tmp | B2055_CAL_RVARCTL, 0x0A);
5044 BWN_RF_WRITE(mac, tmp | B2055_CAL_LPOCTL, 0x40);
5045 BWN_RF_WRITE(mac, tmp | B2055_CAL_TS, 0x55);
5046 BWN_RF_WRITE(mac, tmp | B2055_CAL_RCCALRTS, 0);
5047 BWN_RF_WRITE(mac, tmp | B2055_CAL_RCALRTS, 0);
5049 BWN_RF_WRITE(mac, tmp | B2055_PADDRV, 4);
5050 BWN_RF_WRITE(mac, tmp | B2055_XOCTL1, 1);
5052 BWN_RF_WRITE(mac, tmp | B2055_PADDRV, 0);
5053 BWN_RF_WRITE(mac, tmp | B2055_XOCTL1, 0x2F);
5055 BWN_RF_WRITE(mac, tmp | B2055_XOCTL2, 0);
5057 BWN_RF_WRITE(mac, tmp | B2055_CAL_RVARCTL, 0x06);
5058 BWN_RF_WRITE(mac, tmp | B2055_CAL_LPOCTL, 0x40);
5059 BWN_RF_WRITE(mac, tmp | B2055_CAL_TS, 0x55);
5060 BWN_RF_WRITE(mac, tmp | B2055_CAL_RCCALRTS, 0);
5061 BWN_RF_WRITE(mac, tmp | B2055_CAL_RCALRTS, 0);
5062 BWN_RF_WRITE(mac, tmp | B2055_XOCTL1, 0);
5064 BWN_RF_WRITE(mac, tmp | B2055_PADDRV, 6);
5065 BWN_RF_WRITE(mac, tmp | B2055_XOCTL2,
5066 (mac->mac_phy.rev < 5) ? 0x11 : 0x01);
5068 BWN_RF_WRITE(mac, tmp | B2055_PADDRV, 0);
5069 BWN_RF_WRITE(mac, tmp | B2055_XOCTL2, 0);
5072 BWN_RF_WRITE(mac, tmp | B2055_XOREGUL, 0);
5073 BWN_RF_WRITE(mac, tmp | B2055_XOMISC, 0);
5074 BWN_RF_WRITE(mac, tmp | B2055_PLL_LFC1, 0);
5077 save[0] = BWN_RF_READ(mac, B2055_C1_TX_RF_IQCAL1);
5078 BWN_RF_WRITE(mac, B2055_C1_TX_RF_IQCAL1, 0x29);
5080 save[1] = BWN_RF_READ(mac, B2055_C1_TX_RF_IQCAL2);
5081 BWN_RF_WRITE(mac, B2055_C1_TX_RF_IQCAL2, 0x54);
5083 save[2] = BWN_RF_READ(mac, B2055_C2_TX_RF_IQCAL1);
5084 BWN_RF_WRITE(mac, B2055_C2_TX_RF_IQCAL1, 0x29);
5086 save[3] = BWN_RF_READ(mac, B2055_C2_TX_RF_IQCAL2);
5087 BWN_RF_WRITE(mac, B2055_C2_TX_RF_IQCAL2, 0x54);
5089 save[3] = BWN_RF_READ(mac, B2055_C1_PWRDET_RXTX);
5090 save[4] = BWN_RF_READ(mac, B2055_C2_PWRDET_RXTX);
5092 if (!(BWN_PHY_READ(mac, BWN_NPHY_BANDCTL) &
5094 BWN_RF_WRITE(mac, B2055_C1_PWRDET_RXTX, 0x04);
5095 BWN_RF_WRITE(mac, B2055_C2_PWRDET_RXTX, 0x04);
5097 BWN_RF_WRITE(mac, B2055_C1_PWRDET_RXTX, 0x20);
5098 BWN_RF_WRITE(mac, B2055_C2_PWRDET_RXTX, 0x20);
5101 if (mac->mac_phy.rev < 2) {
5102 BWN_RF_SET(mac, B2055_C1_TX_BB_MXGM, 0x20);
5103 BWN_RF_SET(mac, B2055_C2_TX_BB_MXGM, 0x20);
5105 BWN_RF_MASK(mac, B2055_C1_TX_BB_MXGM, ~0x20);
5106 BWN_RF_MASK(mac, B2055_C2_TX_BB_MXGM, ~0x20);
5112 static void bwn_nphy_update_tx_cal_ladder(struct bwn_mac *mac, uint16_t core)
5114 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5126 bwn_ntab_write(mac, BWN_NTAB16(15, i), entry);
5130 bwn_ntab_write(mac, BWN_NTAB16(15, i + 32), entry);
5134 static void bwn_nphy_pa_set_tx_dig_filter(struct bwn_mac *mac, uint16_t offset,
5142 BWN_PHY_WRITE(mac, offset, filter[i]);
5146 static void bwn_nphy_ext_pa_set_tx_dig_filters(struct bwn_mac *mac)
5148 bwn_nphy_pa_set_tx_dig_filter(mac, 0x2C5,
5153 static void bwn_nphy_int_pa_set_tx_dig_filters(struct bwn_mac *mac)
5165 bwn_nphy_pa_set_tx_dig_filter(mac, offset[i],
5169 if (mac->mac_phy.rev == 16)
5170 bwn_nphy_pa_set_tx_dig_filter(mac, 0x186, dig_filter_phy_rev16);
5173 if (mac->mac_phy.rev == 17) {
5174 bwn_nphy_pa_set_tx_dig_filter(mac, 0x186, dig_filter_phy_rev16);
5175 bwn_nphy_pa_set_tx_dig_filter(mac, 0x195,
5179 if (bwn_is_40mhz(mac)) {
5180 bwn_nphy_pa_set_tx_dig_filter(mac, 0x186,
5183 if (bwn_current_band(mac) == BWN_BAND_5G)
5184 bwn_nphy_pa_set_tx_dig_filter(mac, 0x186,
5186 if (bwn_get_chan(mac) == 14)
5187 bwn_nphy_pa_set_tx_dig_filter(mac, 0x186,
5193 static struct bwn_nphy_txgains bwn_nphy_get_tx_gains(struct bwn_mac *mac)
5195 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5205 bwn_nphy_stay_in_carrier_search(mac, true);
5206 bwn_ntab_read_bulk(mac, BWN_NTAB16(7, 0x110), 2, curr_gain);
5208 bwn_nphy_stay_in_carrier_search(mac, false);
5211 if (mac->mac_phy.rev >= 7) {
5217 } else if (mac->mac_phy.rev >= 3) {
5232 index[0] = (BWN_PHY_READ(mac, BWN_NPHY_C1_TXPCTL_STAT) &
5235 index[1] = (BWN_PHY_READ(mac, BWN_NPHY_C2_TXPCTL_STAT) &
5240 table = bwn_nphy_get_tx_gain_table(mac);
5244 if (mac->mac_phy.rev >= 7) {
5250 } else if (mac->mac_phy.rev >= 3) {
5268 static void bwn_nphy_tx_cal_phy_cleanup(struct bwn_mac *mac)
5270 uint16_t *regs = mac->mac_phy.phy_n->tx_rx_cal_phy_saveregs;
5272 if (mac->mac_phy.rev >= 3) {
5273 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, regs[0]);
5274 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, regs[1]);
5275 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, regs[2]);
5276 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, regs[3]);
5277 BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, regs[4]);
5278 bwn_ntab_write(mac, BWN_NTAB16(8, 3), regs[5]);
5279 bwn_ntab_write(mac, BWN_NTAB16(8, 19), regs[6]);
5280 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, regs[7]);
5281 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, regs[8]);
5282 BWN_PHY_WRITE(mac, BWN_NPHY_PAPD_EN0, regs[9]);
5283 BWN_PHY_WRITE(mac, BWN_NPHY_PAPD_EN1, regs[10]);
5284 bwn_nphy_reset_cca(mac);
5286 BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
5287 BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
5288 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, regs[2]);
5289 bwn_ntab_write(mac, BWN_NTAB16(8, 2), regs[3]);
5290 bwn_ntab_write(mac, BWN_NTAB16(8, 18), regs[4]);
5291 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, regs[5]);
5292 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, regs[6]);
5297 static void bwn_nphy_tx_cal_phy_setup(struct bwn_mac *mac)
5299 struct bwn_phy *phy = &mac->mac_phy;
5300 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5301 uint16_t *regs = mac->mac_phy.phy_n->tx_rx_cal_phy_saveregs;
5304 regs[0] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C1);
5305 regs[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C2);
5306 if (mac->mac_phy.rev >= 3) {
5307 BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
5308 BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
5310 tmp = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER1);
5312 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, tmp | 0x0600);
5314 tmp = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER);
5316 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, tmp | 0x0600);
5318 regs[4] = BWN_PHY_READ(mac, BWN_NPHY_BBCFG);
5319 BWN_PHY_MASK(mac, BWN_NPHY_BBCFG,
5322 tmp = bwn_ntab_read(mac, BWN_NTAB16(8, 3));
5324 bwn_ntab_write(mac, BWN_NTAB16(8, 3), 0);
5326 tmp = bwn_ntab_read(mac, BWN_NTAB16(8, 19));
5328 bwn_ntab_write(mac, BWN_NTAB16(8, 19), 0);
5329 regs[7] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1);
5330 regs[8] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2);
5333 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_PA,
5336 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_PA,
5338 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, 2, 1);
5339 bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, 8, 2);
5341 regs[9] = BWN_PHY_READ(mac, BWN_NPHY_PAPD_EN0);
5342 regs[10] = BWN_PHY_READ(mac, BWN_NPHY_PAPD_EN1);
5343 BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN0, ~0x0001);
5344 BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN1, ~0x0001);
5346 tmp = bwn_nphy_read_lpf_ctl(mac, 0);
5348 bwn_nphy_rf_ctl_override_rev19(mac, 0x80, tmp, 0, false,
5351 bwn_nphy_rf_ctl_override_rev7(mac, 0x80, tmp, 0, false,
5356 bwn_nphy_rf_ctl_override_rev19(mac, 0x8, 0, 0x3,
5359 bwn_nphy_rf_ctl_override_rev7(mac, 0x8, 0, 0x3,
5362 BWN_RF_SETMASK(mac, R2057_OVR_REG0, 1 << 4, 1 << 4);
5363 if (bwn_current_band(mac) == BWN_BAND_2G) {
5364 BWN_RF_SETMASK(mac, R2057_PAD2G_TUNE_PUS_CORE0, ~1, 0);
5365 BWN_RF_SETMASK(mac, R2057_PAD2G_TUNE_PUS_CORE1, ~1, 0);
5367 BWN_RF_SETMASK(mac, R2057_IPA5G_CASCOFFV_PU_CORE0, ~1, 0);
5368 BWN_RF_SETMASK(mac, R2057_IPA5G_CASCOFFV_PU_CORE1, ~1, 0);
5373 BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
5374 BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
5375 tmp = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER);
5377 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, tmp | 0x3000);
5378 tmp = bwn_ntab_read(mac, BWN_NTAB16(8, 2));
5381 bwn_ntab_write(mac, BWN_NTAB16(8, 2), tmp);
5382 tmp = bwn_ntab_read(mac, BWN_NTAB16(8, 18));
5385 bwn_ntab_write(mac, BWN_NTAB16(8, 18), tmp);
5386 regs[5] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1);
5387 regs[6] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2);
5388 if (bwn_current_band(mac) == BWN_BAND_5G)
5392 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, tmp);
5393 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, tmp);
5398 static void bwn_nphy_save_cal(struct bwn_mac *mac)
5400 struct bwn_phy *phy = &mac->mac_phy;
5401 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5409 bwn_nphy_stay_in_carrier_search(mac, 1);
5411 if (bwn_current_band(mac) == BWN_BAND_2G) {
5423 bwn_nphy_rx_iq_coeffs(mac, false, rxcal_coeffs);
5428 txcal_radio_regs[0] = BWN_RF_READ(mac,
5430 txcal_radio_regs[1] = BWN_RF_READ(mac,
5432 txcal_radio_regs[4] = BWN_RF_READ(mac,
5434 txcal_radio_regs[5] = BWN_RF_READ(mac,
5436 txcal_radio_regs[2] = BWN_RF_READ(mac,
5438 txcal_radio_regs[3] = BWN_RF_READ(mac,
5440 txcal_radio_regs[6] = BWN_RF_READ(mac,
5442 txcal_radio_regs[7] = BWN_RF_READ(mac,
5445 txcal_radio_regs[0] = BWN_RF_READ(mac, 0x2021);
5446 txcal_radio_regs[1] = BWN_RF_READ(mac, 0x2022);
5447 txcal_radio_regs[2] = BWN_RF_READ(mac, 0x3021);
5448 txcal_radio_regs[3] = BWN_RF_READ(mac, 0x3022);
5449 txcal_radio_regs[4] = BWN_RF_READ(mac, 0x2023);
5450 txcal_radio_regs[5] = BWN_RF_READ(mac, 0x2024);
5451 txcal_radio_regs[6] = BWN_RF_READ(mac, 0x3023);
5452 txcal_radio_regs[7] = BWN_RF_READ(mac, 0x3024);
5454 txcal_radio_regs[0] = BWN_RF_READ(mac, 0x8B);
5455 txcal_radio_regs[1] = BWN_RF_READ(mac, 0xBA);
5456 txcal_radio_regs[2] = BWN_RF_READ(mac, 0x8D);
5457 txcal_radio_regs[3] = BWN_RF_READ(mac, 0xBC);
5459 iqcal_chanspec->center_freq = bwn_get_centre_freq(mac);
5460 iqcal_chanspec->channel_type = bwn_get_chan_type(mac, NULL);
5461 bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 80), 8, table);
5464 bwn_nphy_stay_in_carrier_search(mac, 0);
5468 static void bwn_nphy_restore_cal(struct bwn_mac *mac)
5470 struct bwn_phy *phy = &mac->mac_phy;
5471 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5481 if (bwn_current_band(mac) == BWN_BAND_2G) {
5493 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 80), 4, table);
5496 if (mac->mac_phy.rev >= 3)
5502 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 88), 4, coef);
5503 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 85), 2, loft);
5504 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 93), 2, loft);
5506 if (mac->mac_phy.rev < 2)
5507 bwn_nphy_tx_iq_workaround(mac);
5509 if (bwn_current_band(mac) == BWN_BAND_2G) {
5521 BWN_RF_WRITE(mac, R2057_TX0_LOFT_FINE_I,
5523 BWN_RF_WRITE(mac, R2057_TX0_LOFT_FINE_Q,
5525 BWN_RF_WRITE(mac, R2057_TX0_LOFT_COARSE_I,
5527 BWN_RF_WRITE(mac, R2057_TX0_LOFT_COARSE_Q,
5529 BWN_RF_WRITE(mac, R2057_TX1_LOFT_FINE_I,
5531 BWN_RF_WRITE(mac, R2057_TX1_LOFT_FINE_Q,
5533 BWN_RF_WRITE(mac, R2057_TX1_LOFT_COARSE_I,
5535 BWN_RF_WRITE(mac, R2057_TX1_LOFT_COARSE_Q,
5538 BWN_RF_WRITE(mac, 0x2021, txcal_radio_regs[0]);
5539 BWN_RF_WRITE(mac, 0x2022, txcal_radio_regs[1]);
5540 BWN_RF_WRITE(mac, 0x3021, txcal_radio_regs[2]);
5541 BWN_RF_WRITE(mac, 0x3022, txcal_radio_regs[3]);
5542 BWN_RF_WRITE(mac, 0x2023, txcal_radio_regs[4]);
5543 BWN_RF_WRITE(mac, 0x2024, txcal_radio_regs[5]);
5544 BWN_RF_WRITE(mac, 0x3023, txcal_radio_regs[6]);
5545 BWN_RF_WRITE(mac, 0x3024, txcal_radio_regs[7]);
5547 BWN_RF_WRITE(mac, 0x8B, txcal_radio_regs[0]);
5548 BWN_RF_WRITE(mac, 0xBA, txcal_radio_regs[1]);
5549 BWN_RF_WRITE(mac, 0x8D, txcal_radio_regs[2]);
5550 BWN_RF_WRITE(mac, 0xBC, txcal_radio_regs[3]);
5552 bwn_nphy_rx_iq_coeffs(mac, true, rxcal_coeffs);
5556 static int bwn_nphy_cal_tx_iq_lo(struct bwn_mac *mac,
5560 struct bwn_phy *phy = &mac->mac_phy;
5561 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5578 bwn_nphy_stay_in_carrier_search(mac, true);
5580 if (mac->mac_phy.rev >= 4) {
5585 bwn_ntab_read_bulk(mac, BWN_NTAB16(7, 0x110), 2, save);
5588 bwn_nphy_iq_cal_gain_params(mac, i, target, ¶ms[i]);
5592 bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x110), 2, gain);
5594 bwn_nphy_tx_cal_radio_setup(mac);
5595 bwn_nphy_tx_cal_phy_setup(mac);
5597 phy6or5x = mac->mac_phy.rev >= 6 ||
5598 (mac->mac_phy.rev == 5 && nphy->ipa2g_on &&
5599 bwn_current_band(mac) == BWN_BAND_2G);
5601 if (bwn_is_40mhz(mac)) {
5602 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 0), 18,
5604 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 32), 18,
5607 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 0), 18,
5609 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 32), 18,
5617 BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x8AD9);
5619 BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
5622 if (!bwn_is_40mhz(mac))
5628 bwn_nphy_run_samples(mac, (bwn_is_40mhz(mac) ? 40 : 20) * 8,
5631 error = bwn_nphy_tx_tone(mac, freq, 250, true, false, false);
5637 if (mac->mac_phy.rev < 3)
5643 if (mac->mac_phy.rev < 3)
5647 if (mac->mac_phy.rev >= 3) {
5657 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 64), length, table);
5660 if (mac->mac_phy.rev >= 3)
5665 if (mac->mac_phy.rev >= 3)
5682 if (mac->mac_phy.rev >= 3)
5687 if (mac->mac_phy.rev >= 3)
5697 bwn_nphy_update_tx_cal_ladder(mac, core);
5702 BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMDNNUM, tmp);
5705 buffer[0] = bwn_ntab_read(mac,
5709 bwn_ntab_write(mac, BWN_NTAB16(15, 69 + core),
5713 BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMD, cmd);
5715 tmp = BWN_PHY_READ(mac, BWN_NPHY_IQLOCAL_CMD);
5721 bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 96), length,
5723 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 64), length,
5733 last = (mac->mac_phy.rev < 3) ? 6 : 7;
5736 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 96), 4, buffer);
5737 bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 80), 4, buffer);
5738 if (mac->mac_phy.rev < 3) {
5744 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 88), 4,
5746 bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 101), 2,
5748 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 85), 2,
5750 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 93), 2,
5753 if (mac->mac_phy.rev < 3)
5755 bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 96), length,
5759 bwn_get_centre_freq(mac);
5760 nphy->txiqlocal_chanspec.channel_type = bwn_get_chan_type(mac, NULL);
5763 if (mac->mac_phy.rev < 3)
5765 bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 96), length,
5769 bwn_nphy_stop_playback(mac);
5770 BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0);
5773 bwn_nphy_tx_cal_phy_cleanup(mac);
5774 bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x110), 2, save);
5776 if (mac->mac_phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
5777 bwn_nphy_tx_iq_workaround(mac);
5779 if (mac->mac_phy.rev >= 4)
5782 bwn_nphy_stay_in_carrier_search(mac, false);
5788 static void bwn_nphy_reapply_tx_cal_coeffs(struct bwn_mac *mac)
5790 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5796 nphy->txiqlocal_chanspec.center_freq != bwn_get_centre_freq(mac) ||
5797 nphy->txiqlocal_chanspec.channel_type != bwn_get_chan_type(mac, NULL))
5800 bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 80), 7, buffer);
5809 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 80), 4,
5813 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 88), 4,
5815 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 85), 2,
5817 bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 93), 2,
5823 static int bwn_nphy_rev2_cal_rx_iq(struct bwn_mac *mac,
5826 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
5849 bwn_nphy_stay_in_carrier_search(mac, 1);
5851 if (mac->mac_phy.rev < 2)
5852 bwn_nphy_reapply_tx_cal_coeffs(mac);
5853 bwn_ntab_read_bulk(mac, BWN_NTAB16(7, 0x110), 2, gain_save);
5855 bwn_nphy_iq_cal_gain_params(mac, i, target, &cal_params[i]);
5858 bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x110), 2, cal_gain);
5871 tmp[1] = BWN_PHY_READ(mac, BWN_NPHY_RFSEQCA);
5872 tmp[2] = BWN_PHY_READ(mac, afectl_core);
5873 tmp[3] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER);
5874 tmp[4] = BWN_PHY_READ(mac, rfctl[0]);
5875 tmp[5] = BWN_PHY_READ(mac, rfctl[1]);
5877 BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA,
5880 BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_TXEN,
5882 BWN_PHY_SET(mac, afectl_core, 0x0006);
5883 BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x0006);
5885 band = bwn_current_band(mac);
5889 BWN_PHY_WRITE(mac, rfctl[0], 0x140);
5891 BWN_PHY_WRITE(mac, rfctl[0], 0x110);
5894 BWN_PHY_WRITE(mac, rfctl[0], 0x180);
5896 BWN_PHY_WRITE(mac, rfctl[0], 0x120);
5900 BWN_PHY_WRITE(mac, rfctl[1], 0x148);
5902 BWN_PHY_WRITE(mac, rfctl[1], 0x114);
5905 BWN_RF_SETMASK(mac, B2055_C1_GENSPARE2, 0xFC,
5907 BWN_RF_SETMASK(mac, B2055_C2_GENSPARE2, 0xFC,
5945 bwn_nphy_rf_ctl_override(mac, 0x400, tmp[0], 3,
5947 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX);
5948 bwn_nphy_stop_playback(mac);
5951 ret = bwn_nphy_tx_tone(mac, 4000,
5956 bwn_nphy_run_samples(mac, 160, 0xFFFF, 0, false,
5962 bwn_nphy_rx_iq_est(mac, &est, 1024, 32,
5973 bwn_nphy_calc_rx_iq_comp(mac, 1 << i);
5975 bwn_nphy_stop_playback(mac);
5982 BWN_RF_MASK(mac, B2055_C1_GENSPARE2, 0xFC);
5983 BWN_RF_MASK(mac, B2055_C2_GENSPARE2, 0xFC);
5984 BWN_PHY_WRITE(mac, rfctl[1], tmp[5]);
5985 BWN_PHY_WRITE(mac, rfctl[0], tmp[4]);
5986 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, tmp[3]);
5987 BWN_PHY_WRITE(mac, afectl_core, tmp[2]);
5988 BWN_PHY_WRITE(mac, BWN_NPHY_RFSEQCA, tmp[1]);
5994 bwn_nphy_rf_ctl_override(mac, 0x400, 0, 3, true);
5995 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX);
5996 bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x110), 2, gain_save);
5998 bwn_nphy_stay_in_carrier_search(mac, 0);
6003 static int bwn_nphy_rev3_cal_rx_iq(struct bwn_mac *mac,
6010 static int bwn_nphy_cal_rx_iq(struct bwn_mac *mac,
6013 if (mac->mac_phy.rev >= 7)
6016 if (mac->mac_phy.rev >= 3)
6017 return bwn_nphy_rev3_cal_rx_iq(mac, target, type, debug);
6019 return bwn_nphy_rev2_cal_rx_iq(mac, target, type, debug);
6023 static void bwn_nphy_set_rx_core_state(struct bwn_mac *mac, uint8_t mask)
6025 struct bwn_phy *phy = &mac->mac_phy;
6034 bwn_mac_suspend(mac);
6037 bwn_nphy_stay_in_carrier_search(mac, true);
6039 BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_RXEN,
6043 BWN_PHY_WRITE(mac, BWN_NPHY_HPANT_SWTHRES, 1);
6044 if (mac->mac_phy.rev >= 3) {
6048 BWN_PHY_WRITE(mac, BWN_NPHY_HPANT_SWTHRES, 0x1E);
6049 if (mac->mac_phy.rev >= 3) {
6054 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX);
6057 bwn_nphy_stay_in_carrier_search(mac, false);
6059 bwn_mac_enable(mac);
6063 bwn_nphy_op_recalc_txpower(struct bwn_mac *mac, bool ignore_tssi)
6065 struct bwn_phy *phy = &mac->mac_phy;
6066 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
6067 struct ieee80211_channel *channel = bwn_get_channel(mac);
6068 struct bwn_softc *sc = mac->mac_sc;
6072 if (nphy->tx_pwr_last_recalc_freq == bwn_get_centre_freq(mac) &&
6077 bwn_ppr_clear(mac, ppr);
6080 bwn_ppr_load_max_from_sprom(mac, ppr, BWN_PHY_BAND_2G);
6084 max = INT_TO_Q52(bwn_get_chan_power(mac, channel));
6088 bwn_ppr_apply_max(mac, ppr, max);
6089 DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT_POWER,
6091 Q52_ARG(bwn_ppr_get_max(mac, ppr)));
6097 if (bwn_current_band(mac) == BWN_BAND_2G)
6101 bwn_ppr_add(mac, ppr, -hw_gain);
6105 bwn_ppr_apply_min(mac, ppr, INT_TO_Q52(8));
6108 bwn_mac_suspend(mac);
6109 bwn_nphy_tx_power_ctl_setup(mac);
6111 BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0, BWN_MACCTL_PHY_LOCK);
6112 BWN_READ_4(mac, BWN_MACCTL);
6115 bwn_nphy_tx_power_ctrl(mac, nphy->txpwrctrl);
6117 BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~BWN_MACCTL_PHY_LOCK, 0);
6118 bwn_mac_enable(mac);
6120 nphy->tx_pwr_last_recalc_freq = bwn_get_centre_freq(mac);
6131 static void bwn_nphy_update_mimo_config(struct bwn_mac *mac, int32_t preamble)
6133 uint16_t mimocfg = BWN_PHY_READ(mac, BWN_NPHY_MIMOCFG);
6141 BWN_PHY_WRITE(mac, BWN_NPHY_MIMOCFG, mimocfg);
6145 static void bwn_nphy_bphy_init(struct bwn_mac *mac)
6152 BWN_PHY_WRITE(mac, BWN_PHY_N_BMODE(0x88 + i), val);
6157 BWN_PHY_WRITE(mac, BWN_PHY_N_BMODE(0x98 + i), val);
6160 BWN_PHY_WRITE(mac, BWN_PHY_N_BMODE(0x38), 0x668);
6164 static int bwn_nphy_superswitch_init(struct bwn_mac *mac, bool init)
6168 if (mac->mac_phy.rev >= 7)
6171 if (mac->mac_phy.rev >= 3) {
6175 bwn_ntab_write(mac, BWN_NTAB16(9, 2), 0x211);
6176 bwn_ntab_write(mac, BWN_NTAB16(9, 3), 0x222);
6177 bwn_ntab_write(mac, BWN_NTAB16(9, 8), 0x144);
6178 bwn_ntab_write(mac, BWN_NTAB16(9, 12), 0x188);
6181 BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_LOOEN, 0);
6182 BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_HIOEN, 0);
6184 if ((error = bwn_gpio_control(mac, 0xfc00)))
6187 BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~BWN_MACCTL_GPOUT_MASK, 0);
6188 BWN_WRITE_SETMASK2(mac, BWN_GPIO_MASK, ~0, 0xFC00);
6189 BWN_WRITE_SETMASK2(mac, BWN_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
6193 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
6194 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
6195 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
6196 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
6204 static int bwn_phy_initn(struct bwn_mac *mac)
6206 struct bwn_softc *sc = mac->mac_sc;
6207 struct bwn_phy *phy = &mac->mac_phy;
6218 if (mac->mac_phy.rev >= 3) {
6222 BWN_ERRPRINTF(mac->mac_sc, "Error reading %s from "
6230 if ((mac->mac_phy.rev >= 3) &&
6232 (bwn_current_band(mac) == BWN_BAND_2G))
6236 nphy->use_int_tx_iq_lo_cal = bwn_nphy_ipa(mac) ||
6241 bwn_nphy_tables_init(mac);
6246 if (mac->mac_phy.rev >= 3) {
6247 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S1, 0);
6248 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_OVER, 0);
6250 BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER3, 0);
6251 BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER4, 0);
6252 BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER5, 0);
6253 BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER6, 0);
6259 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S0, 0);
6260 BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B32S1, 0);
6262 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_OVER, 0);
6264 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, 0);
6265 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, 0);
6266 if (mac->mac_phy.rev < 6) {
6267 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC3, 0);
6268 BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC4, 0);
6270 BWN_PHY_MASK(mac, BWN_NPHY_RFSEQMODE,
6273 if (mac->mac_phy.rev >= 3)
6274 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, 0);
6275 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, 0);
6277 if (mac->mac_phy.rev <= 2) {
6278 tmp = (mac->mac_phy.rev == 2) ? 0x3B : 0x40;
6279 BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3,
6283 BWN_PHY_WRITE(mac, BWN_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
6284 BWN_PHY_WRITE(mac, BWN_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
6289 BWN_PHY_WRITE(mac, BWN_NPHY_TXREALFD, 0xA0);
6291 BWN_PHY_WRITE(mac, BWN_NPHY_TXREALFD, 0xB8);
6292 BWN_PHY_WRITE(mac, BWN_NPHY_MIMO_CRSTXEXT, 0xC8);
6293 BWN_PHY_WRITE(mac, BWN_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
6294 BWN_PHY_WRITE(mac, BWN_NPHY_TXRIFS_FRDEL, 0x30);
6297 bwn_nphy_update_mimo_config(mac, nphy->preamble_override);
6299 bwn_nphy_update_txrx_chain(mac);
6302 BWN_PHY_WRITE(mac, BWN_NPHY_DUP40_GFBL, 0xAA8);
6303 BWN_PHY_WRITE(mac, BWN_NPHY_DUP40_BL, 0x9A4);
6306 if (bwn_nphy_ipa(mac)) {
6307 BWN_PHY_SET(mac, BWN_NPHY_PAPD_EN0, 0x1);
6308 BWN_PHY_SETMASK(mac, BWN_NPHY_EPS_TABLE_ADJ0, 0x007F,
6310 BWN_PHY_SET(mac, BWN_NPHY_PAPD_EN1, 0x1);
6311 BWN_PHY_SETMASK(mac, BWN_NPHY_EPS_TABLE_ADJ1, 0x007F,
6313 bwn_nphy_int_pa_set_tx_dig_filters(mac);
6315 bwn_nphy_ext_pa_set_tx_dig_filters(mac);
6318 if ((error = bwn_nphy_workarounds(mac)))
6322 bwn_phy_force_clock(mac, 1);
6323 tmp = BWN_PHY_READ(mac, BWN_NPHY_BBCFG);
6324 BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, tmp | BWN_NPHY_BBCFG_RSTCCA);
6325 BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, tmp & ~BWN_NPHY_BBCFG_RSTCCA);
6326 bwn_phy_force_clock(mac, 0);
6328 bwn_mac_phy_clock_set(mac, true);
6331 bwn_nphy_pa_override(mac, false);
6332 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RX2TX);
6333 bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX);
6334 bwn_nphy_pa_override(mac, true);
6337 bwn_nphy_classifier(mac, 0, 0);
6338 bwn_nphy_read_clip_detection(mac, clip);
6339 if (bwn_current_band(mac) == BWN_BAND_2G)
6340 bwn_nphy_bphy_init(mac);
6343 bwn_nphy_tx_power_ctrl(mac, false);
6344 if ((error = bwn_nphy_tx_power_fix(mac)))
6346 bwn_nphy_tx_power_ctl_idle_tssi(mac);
6347 bwn_nphy_tx_power_ctl_setup(mac);
6348 bwn_nphy_tx_gain_table_upload(mac);
6351 bwn_nphy_set_rx_core_state(mac, nphy->phyrxchain);
6357 if (bwn_current_band(mac) == BWN_BAND_2G)
6363 bwn_nphy_rssi_cal(mac);
6365 bwn_nphy_restore_rssi_cal(mac);
6367 bwn_nphy_rssi_cal(mac);
6371 if (bwn_current_band(mac) == BWN_BAND_2G)
6380 target = bwn_nphy_get_tx_gains(mac);
6383 error = bwn_nphy_superswitch_init(mac, true);
6388 bwn_nphy_rssi_cal(mac);
6395 target = bwn_nphy_get_tx_gains(mac);
6397 if (!bwn_nphy_cal_tx_iq_lo(mac, target, true, false))
6398 if (bwn_nphy_cal_rx_iq(mac, target, 2, 0) == 0)
6399 bwn_nphy_save_cal(mac);
6403 bwn_nphy_restore_cal(mac);
6407 bwn_nphy_tx_pwr_ctrl_coef_setup(mac);
6408 bwn_nphy_tx_power_ctrl(mac, tx_pwr_state);
6409 BWN_PHY_WRITE(mac, BWN_NPHY_TXMACIF_HOLDOFF, 0x0015);
6410 BWN_PHY_WRITE(mac, BWN_NPHY_TXMACDELAY, 0x0320);
6412 BWN_PHY_WRITE(mac, BWN_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032);
6413 bwn_nphy_tx_lpf_bw(mac);
6415 bwn_nphy_spur_workaround(mac);
6424 static void bwn_chantab_phy_upload(struct bwn_mac *mac,
6427 BWN_PHY_WRITE(mac, BWN_NPHY_BW1A, e->phy_bw1a);
6428 BWN_PHY_WRITE(mac, BWN_NPHY_BW2, e->phy_bw2);
6429 BWN_PHY_WRITE(mac, BWN_NPHY_BW3, e->phy_bw3);
6430 BWN_PHY_WRITE(mac, BWN_NPHY_BW4, e->phy_bw4);
6431 BWN_PHY_WRITE(mac, BWN_NPHY_BW5, e->phy_bw5);
6432 BWN_PHY_WRITE(mac, BWN_NPHY_BW6, e->phy_bw6);
6436 static void bwn_nphy_pmu_spur_avoid(struct bwn_mac *mac,
6439 struct bwn_softc *sc = mac->mac_sc;
6445 BWN_ERRPRINTF(mac->mac_sc, "no PMU; cannot configure spurious "
6457 static int bwn_nphy_channel_setup(struct bwn_mac *mac,
6461 struct bwn_softc *sc = mac->mac_sc;
6462 struct bwn_phy *phy = &mac->mac_phy;
6463 struct bwn_phy_n *nphy = mac->mac_phy.phy_n;
6468 if (bwn_channel_band(mac, new_channel) == BWN_BAND_5G) {
6471 BWN_PHY_MASK(mac, BWN_NPHY_BANDCTL, ~BWN_NPHY_BANDCTL_5GHZ);
6473 tmp16 = BWN_READ_2(mac, BWN_PSM_PHY_HDR);
6474 BWN_WRITE_2(mac, BWN_PSM_PHY_HDR, tmp16 | 4);
6476 BWN_PHY_SET(mac, BWN_PHY_B_BBCFG,
6478 BWN_WRITE_2(mac, BWN_PSM_PHY_HDR, tmp16);
6479 BWN_PHY_SET(mac, BWN_NPHY_BANDCTL, BWN_NPHY_BANDCTL_5GHZ);
6480 } else if (bwn_channel_band(mac, new_channel) == BWN_BAND_2G) {
6482 BWN_PHY_MASK(mac, BWN_NPHY_BANDCTL, ~BWN_NPHY_BANDCTL_5GHZ);
6483 tmp16 = BWN_READ_2(mac, BWN_PSM_PHY_HDR);
6484 BWN_WRITE_2(mac, BWN_PSM_PHY_HDR, tmp16 | 4);
6486 BWN_PHY_MASK(mac, BWN_PHY_B_BBCFG,
6488 BWN_WRITE_2(mac, BWN_PSM_PHY_HDR, tmp16);
6490 BWN_ERRPRINTF(mac->mac_sc, "%s: unknown band?\n", __func__);
6493 bwn_chantab_phy_upload(mac, e);
6496 bwn_nphy_classifier(mac, 2, 0);
6497 BWN_PHY_SET(mac, BWN_PHY_B_TEST, 0x0800);
6499 bwn_nphy_classifier(mac, 2, 2);
6500 if (bwn_channel_band(mac, new_channel) == BWN_BAND_2G)
6501 BWN_PHY_MASK(mac, BWN_PHY_B_TEST, ~0x840);
6505 if ((error = bwn_nphy_tx_power_fix(mac)))
6509 if (mac->mac_phy.rev < 3)
6510 bwn_nphy_adjust_lna_gain_table(mac);
6512 bwn_nphy_tx_lpf_bw(mac);
6514 if (mac->mac_phy.rev >= 3 &&
6515 mac->mac_phy.phy_n->spur_avoid != BWN_SPUR_AVOID_DISABLE) {
6518 if (mac->mac_phy.phy_n->spur_avoid == BWN_SPUR_AVOID_FORCE) {
6529 if (!bwn_is_40mhz(mac)) { /* 20MHz */
6537 if (!bwn_is_40mhz(mac)) { /* 20MHz */
6548 bwn_nphy_pmu_spur_avoid(mac, spuravoid);
6550 bwn_mac_switch_freq(mac, spuravoid);
6552 if (mac->mac_phy.rev == 3 || mac->mac_phy.rev == 4)
6553 bwn_wireless_core_phy_pll_reset(mac);
6556 BWN_PHY_SET(mac, BWN_NPHY_BBCFG, BWN_NPHY_BBCFG_RSTRX);
6558 BWN_PHY_MASK(mac, BWN_NPHY_BBCFG,
6561 bwn_nphy_reset_cca(mac);
6566 BWN_PHY_WRITE(mac, BWN_NPHY_NDATAT_DUP40, 0x3830);
6569 bwn_nphy_spur_workaround(mac);
6575 static int bwn_nphy_set_channel(struct bwn_mac *mac,
6579 struct bwn_phy *phy = &mac->mac_phy;
6593 r2057_get_chantabent_rev7(mac, bwn_get_chan_centre_freq(mac, channel),
6598 tabent_r3 = bwn_nphy_get_chantabent_rev3(mac,
6599 bwn_get_chan_centre_freq(mac, channel));
6603 tabent_r2 = bwn_nphy_get_chantabent_rev2(mac,
6622 BWN_PHY_SET(mac, BWN_NPHY_RXCTL, BWN_NPHY_RXCTL_BSELU20);
6624 BWN_PHY_SET(mac, 0x310, 0x8000);
6626 BWN_PHY_MASK(mac, BWN_NPHY_RXCTL, ~BWN_NPHY_RXCTL_BSELU20);
6628 BWN_PHY_MASK(mac, 0x310, (uint16_t)~0x8000);
6639 tmp = (bwn_channel_band(mac, channel) == BWN_BAND_5G) ? 2 : 0;
6640 BWN_RF_SETMASK(mac, R2057_TIA_CONFIG_CORE0, ~2, tmp);
6641 BWN_RF_SETMASK(mac, R2057_TIA_CONFIG_CORE1, ~2, tmp);
6644 bwn_radio_2057_setup(mac, tabent_r7, tabent_r7_2g);
6645 error = bwn_nphy_channel_setup(mac, phy_regs, channel);
6647 tmp = (bwn_channel_band(mac, channel) == BWN_BAND_5G) ? 4 : 0;
6648 BWN_RF_SETMASK(mac, 0x08, 0xFFFB, tmp);
6649 bwn_radio_2056_setup(mac, tabent_r3);
6650 error = bwn_nphy_channel_setup(mac, &(tabent_r3->phy_regs),
6653 tmp = (bwn_channel_band(mac, channel) == BWN_BAND_5G) ? 0x0020 : 0x0050;
6654 BWN_RF_SETMASK(mac, B2055_MASTER1, 0xFF8F, tmp);
6655 bwn_radio_2055_setup(mac, tabent_r2);
6656 error = bwn_nphy_channel_setup(mac, &(tabent_r2->phy_regs),
6668 bwn_nphy_op_allocate(struct bwn_mac *mac)
6676 mac->mac_phy.phy_n = nphy;
6682 bwn_nphy_op_prepare_structs(struct bwn_mac *mac)
6684 struct bwn_softc *sc = mac->mac_sc;
6685 struct bwn_phy *phy = &mac->mac_phy;
6706 if (mac->mac_phy.rev >= 3 ||
6712 if (mac->mac_phy.rev >= 2 &&
6723 if (mac->mac_phy.rev >= 3) {
6729 BWN_ERRPRINTF(mac->mac_sc, "Error reading 2GHz EPA "
6737 BWN_ERRPRINTF(mac->mac_sc, "Error reading 5GHz EPA "
6750 bwn_nphy_op_free(struct bwn_mac *mac)
6752 struct bwn_phy *phy = &mac->mac_phy;
6760 bwn_nphy_op_init(struct bwn_mac *mac)
6762 return bwn_phy_initn(mac);
6765 static inline void check_phyreg(struct bwn_mac *mac, uint16_t offset)
6770 BWN_ERRPRINTF(mac->mac_sc, "Invalid OFDM PHY access at "
6775 BWN_ERRPRINTF(mac->mac_sc, "Invalid EXT-G PHY access at "
6782 bwn_nphy_op_maskset(struct bwn_mac *mac, uint16_t reg, uint16_t mask,
6785 check_phyreg(mac, reg);
6786 BWN_WRITE_2_F(mac, BWN_PHYCTL, reg);
6787 BWN_WRITE_SETMASK2(mac, BWN_PHYDATA, mask, set);
6792 bwn_nphy_op_radio_read(struct bwn_mac *mac, uint16_t reg)
6795 if (mac->mac_phy.rev < 7 && reg == 1) {
6796 BWN_ERRPRINTF(mac->mac_sc, "%s: bad reg access\n", __func__);
6799 if (mac->mac_phy.rev >= 7)
6804 BWN_WRITE_2_F(mac, BWN_RFCTL, reg);
6805 return BWN_READ_2(mac, BWN_RFDATALO);
6811 bwn_nphy_op_radio_write(struct bwn_mac *mac, uint16_t reg, uint16_t value)
6814 if (mac->mac_phy.rev < 7 && reg == 1) {
6815 BWN_ERRPRINTF(mac->mac_sc, "%s: bad reg access\n", __func__);
6818 BWN_WRITE_2_F(mac, BWN_RFCTL, reg);
6819 BWN_WRITE_2(mac, BWN_RFDATALO, value);
6825 bwn_nphy_op_software_rfkill(struct bwn_mac *mac, bool active)
6827 struct bwn_phy *phy = &mac->mac_phy;
6829 if (BWN_READ_4(mac, BWN_MACCTL) & BWN_MACCTL_ON)
6830 BWN_ERRPRINTF(mac->mac_sc, "MAC not suspended\n");
6832 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET | BWN_DEBUG_PHY,
6834 phy->rev, mac->mac_phy.rf_on, active);
6846 // if (!mac->mac_phy.rf_on)
6847 bwn_radio_2057_init(mac);
6848 bwn_switch_channel(mac, bwn_get_chan(mac));
6850 // if (!mac->mac_phy.rf_on)
6851 bwn_radio_init2056(mac);
6852 bwn_switch_channel(mac, bwn_get_chan(mac));
6854 bwn_radio_init2055(mac);
6860 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD,
6865 BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD,
6868 BWN_RF_MASK(mac, 0x09, ~0x2);
6870 BWN_RF_WRITE(mac, 0x204D, 0);
6871 BWN_RF_WRITE(mac, 0x2053, 0);
6872 BWN_RF_WRITE(mac, 0x2058, 0);
6873 BWN_RF_WRITE(mac, 0x205E, 0);
6874 BWN_RF_MASK(mac, 0x2062, ~0xF0);
6875 BWN_RF_WRITE(mac, 0x2064, 0);
6877 BWN_RF_WRITE(mac, 0x304D, 0);
6878 BWN_RF_WRITE(mac, 0x3053, 0);
6879 BWN_RF_WRITE(mac, 0x3058, 0);
6880 BWN_RF_WRITE(mac, 0x305E, 0);
6881 BWN_RF_MASK(mac, 0x3062, ~0xF0);
6882 BWN_RF_WRITE(mac, 0x3064, 0);
6889 bwn_nphy_op_switch_analog(struct bwn_mac *mac, bool on)
6891 struct bwn_phy *phy = &mac->mac_phy;
6897 device_printf(mac->mac_sc->sc_dev, "%s: TODO\n", __func__);
6900 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, core);
6901 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, override);
6902 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, core);
6903 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, override);
6905 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, override);
6906 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, core);
6907 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, override);
6908 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, core);
6911 BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, override);
6916 bwn_nphy_op_switch_channel(struct bwn_mac *mac, unsigned int new_channel)
6918 struct ieee80211_channel *channel = bwn_get_channel(mac);
6919 bwn_chan_type_t channel_type = bwn_get_chan_type(mac, NULL);
6921 if (bwn_current_band(mac) == BWN_BAND_2G) {
6929 return bwn_nphy_set_channel(mac, channel, channel_type);
6934 bwn_nphy_op_get_default_chan(struct bwn_mac *mac)
6936 if (bwn_current_band(mac) == BWN_BAND_2G)