Lines Matching refs:sc
237 vge_eeprom_getword(struct vge_softc *sc, int addr, uint16_t *dest)
247 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
248 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
251 CSR_WRITE_1(sc, VGE_EEADDR, addr);
254 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD);
258 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)
263 device_printf(sc->vge_dev, "EEPROM read timed out\n");
269 word = CSR_READ_2(sc, VGE_EERDDAT);
272 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
273 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
283 vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, int swap)
290 vge_eeprom_getword(sc, off + i, &word);
299 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i);
304 vge_miipoll_stop(struct vge_softc *sc)
308 CSR_WRITE_1(sc, VGE_MIICMD, 0);
312 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
317 device_printf(sc->vge_dev, "failed to idle MII autopoll\n");
321 vge_miipoll_start(struct vge_softc *sc)
327 CSR_WRITE_1(sc, VGE_MIICMD, 0);
328 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);
332 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
337 device_printf(sc->vge_dev, "failed to idle MII autopoll\n");
343 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);
349 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)
354 device_printf(sc->vge_dev, "failed to start MII autopoll\n");
360 struct vge_softc *sc;
364 sc = device_get_softc(dev);
366 vge_miipoll_stop(sc);
369 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
372 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD);
377 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)
382 device_printf(sc->vge_dev, "MII read timed out\n");
384 rval = CSR_READ_2(sc, VGE_MIIDATA);
386 vge_miipoll_start(sc);
394 struct vge_softc *sc;
397 sc = device_get_softc(dev);
399 vge_miipoll_stop(sc);
402 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
405 CSR_WRITE_2(sc, VGE_MIIDATA, data);
408 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD);
413 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0)
418 device_printf(sc->vge_dev, "MII write timed out\n");
422 vge_miipoll_start(sc);
428 vge_cam_clear(struct vge_softc *sc)
438 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
439 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
440 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);
442 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
446 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0);
448 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
450 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
451 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
452 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
454 sc->vge_camidx = 0;
458 vge_cam_set(struct vge_softc *sc, uint8_t *addr)
462 if (sc->vge_camidx == VGE_CAM_MAXADDRS)
466 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
467 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA);
470 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx);
474 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]);
477 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE);
482 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0)
487 device_printf(sc->vge_dev, "setting CAM filter failed\n");
493 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
494 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
497 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8),
498 1<<(sc->vge_camidx & 7));
500 sc->vge_camidx++;
504 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
505 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
506 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
512 vge_setvlan(struct vge_softc *sc)
517 VGE_LOCK_ASSERT(sc);
519 ifp = sc->vge_ifp;
520 cfg = CSR_READ_1(sc, VGE_RXCFG);
525 CSR_WRITE_1(sc, VGE_RXCFG, cfg);
531 struct vge_softc *sc = arg;
533 if (sc->vge_camidx == VGE_CAM_MAXADDRS)
536 (void )vge_cam_set(sc, LLADDR(sdl));
561 vge_rxfilter(struct vge_softc *sc)
567 VGE_LOCK_ASSERT(sc);
573 rxcfg = CSR_READ_1(sc, VGE_RXCTL);
582 ifp = sc->vge_ifp;
595 vge_cam_clear(sc);
598 if_foreach_llmaddr(ifp, vge_set_maddr, sc);
601 if (sc->vge_camidx == VGE_CAM_MAXADDRS) {
602 vge_cam_clear(sc);
609 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]);
610 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]);
611 CSR_WRITE_1(sc, VGE_RXCTL, rxcfg);
615 vge_reset(struct vge_softc *sc)
619 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET);
623 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0)
628 device_printf(sc->vge_dev, "soft reset timed out\n");
629 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE);
682 vge_dma_alloc(struct vge_softc *sc)
698 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0)
705 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */
715 &sc->vge_cdata.vge_ring_tag);
717 device_printf(sc->vge_dev,
723 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */
733 &sc->vge_cdata.vge_tx_ring_tag);
735 device_printf(sc->vge_dev,
741 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */
751 &sc->vge_cdata.vge_rx_ring_tag);
753 device_printf(sc->vge_dev,
759 error = bus_dmamem_alloc(sc->vge_cdata.vge_tx_ring_tag,
760 (void **)&sc->vge_rdata.vge_tx_ring,
762 &sc->vge_cdata.vge_tx_ring_map);
764 device_printf(sc->vge_dev,
770 error = bus_dmamap_load(sc->vge_cdata.vge_tx_ring_tag,
771 sc->vge_cdata.vge_tx_ring_map, sc->vge_rdata.vge_tx_ring,
774 device_printf(sc->vge_dev,
778 sc->vge_rdata.vge_tx_ring_paddr = ctx.vge_busaddr;
781 error = bus_dmamem_alloc(sc->vge_cdata.vge_rx_ring_tag,
782 (void **)&sc->vge_rdata.vge_rx_ring,
784 &sc->vge_cdata.vge_rx_ring_map);
786 device_printf(sc->vge_dev,
792 error = bus_dmamap_load(sc->vge_cdata.vge_rx_ring_tag,
793 sc->vge_cdata.vge_rx_ring_map, sc->vge_rdata.vge_rx_ring,
796 device_printf(sc->vge_dev,
800 sc->vge_rdata.vge_rx_ring_paddr = ctx.vge_busaddr;
803 tx_ring_end = sc->vge_rdata.vge_tx_ring_paddr + VGE_TX_LIST_SZ;
804 rx_ring_end = sc->vge_rdata.vge_rx_ring_paddr + VGE_RX_LIST_SZ;
806 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)) ||
808 VGE_ADDR_HI(sc->vge_rdata.vge_rx_ring_paddr)) ||
810 device_printf(sc->vge_dev, "4GB boundary crossed, "
812 vge_dma_free(sc);
818 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0)
823 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */
833 &sc->vge_cdata.vge_buffer_tag);
835 device_printf(sc->vge_dev,
841 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */
851 &sc->vge_cdata.vge_tx_tag);
853 device_printf(sc->vge_dev, "could not create Tx DMA tag.\n");
858 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */
868 &sc->vge_cdata.vge_rx_tag);
870 device_printf(sc->vge_dev, "could not create Rx DMA tag.\n");
876 txd = &sc->vge_cdata.vge_txdesc[i];
879 error = bus_dmamap_create(sc->vge_cdata.vge_tx_tag, 0,
882 device_printf(sc->vge_dev,
888 if ((error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0,
889 &sc->vge_cdata.vge_rx_sparemap)) != 0) {
890 device_printf(sc->vge_dev,
895 rxd = &sc->vge_cdata.vge_rxdesc[i];
898 error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0,
901 device_printf(sc->vge_dev,
912 vge_dma_free(struct vge_softc *sc)
919 if (sc->vge_cdata.vge_tx_ring_tag != NULL) {
920 if (sc->vge_rdata.vge_tx_ring_paddr)
921 bus_dmamap_unload(sc->vge_cdata.vge_tx_ring_tag,
922 sc->vge_cdata.vge_tx_ring_map);
923 if (sc->vge_rdata.vge_tx_ring)
924 bus_dmamem_free(sc->vge_cdata.vge_tx_ring_tag,
925 sc->vge_rdata.vge_tx_ring,
926 sc->vge_cdata.vge_tx_ring_map);
927 sc->vge_rdata.vge_tx_ring = NULL;
928 sc->vge_rdata.vge_tx_ring_paddr = 0;
929 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_ring_tag);
930 sc->vge_cdata.vge_tx_ring_tag = NULL;
933 if (sc->vge_cdata.vge_rx_ring_tag != NULL) {
934 if (sc->vge_rdata.vge_rx_ring_paddr)
935 bus_dmamap_unload(sc->vge_cdata.vge_rx_ring_tag,
936 sc->vge_cdata.vge_rx_ring_map);
937 if (sc->vge_rdata.vge_rx_ring)
938 bus_dmamem_free(sc->vge_cdata.vge_rx_ring_tag,
939 sc->vge_rdata.vge_rx_ring,
940 sc->vge_cdata.vge_rx_ring_map);
941 sc->vge_rdata.vge_rx_ring = NULL;
942 sc->vge_rdata.vge_rx_ring_paddr = 0;
943 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_ring_tag);
944 sc->vge_cdata.vge_rx_ring_tag = NULL;
947 if (sc->vge_cdata.vge_tx_tag != NULL) {
949 txd = &sc->vge_cdata.vge_txdesc[i];
951 bus_dmamap_destroy(sc->vge_cdata.vge_tx_tag,
956 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_tag);
957 sc->vge_cdata.vge_tx_tag = NULL;
960 if (sc->vge_cdata.vge_rx_tag != NULL) {
962 rxd = &sc->vge_cdata.vge_rxdesc[i];
964 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag,
969 if (sc->vge_cdata.vge_rx_sparemap != NULL) {
970 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag,
971 sc->vge_cdata.vge_rx_sparemap);
972 sc->vge_cdata.vge_rx_sparemap = NULL;
974 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_tag);
975 sc->vge_cdata.vge_rx_tag = NULL;
978 if (sc->vge_cdata.vge_buffer_tag != NULL) {
979 bus_dma_tag_destroy(sc->vge_cdata.vge_buffer_tag);
980 sc->vge_cdata.vge_buffer_tag = NULL;
982 if (sc->vge_cdata.vge_ring_tag != NULL) {
983 bus_dma_tag_destroy(sc->vge_cdata.vge_ring_tag);
984 sc->vge_cdata.vge_ring_tag = NULL;
996 struct vge_softc *sc;
1000 sc = device_get_softc(dev);
1001 sc->vge_dev = dev;
1003 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1005 callout_init_mtx(&sc->vge_watchdog, &sc->vge_mtx, 0);
1013 sc->vge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1016 if (sc->vge_res == NULL) {
1023 sc->vge_flags |= VGE_FLAG_PCIE;
1024 sc->vge_expcap = cap;
1026 sc->vge_flags |= VGE_FLAG_JUMBO;
1028 sc->vge_flags |= VGE_FLAG_PMCAP;
1029 sc->vge_pmcap = cap;
1037 sc->vge_flags |= VGE_FLAG_MSI;
1047 sc->vge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1048 ((sc->vge_flags & VGE_FLAG_MSI) ? 0 : RF_SHAREABLE) | RF_ACTIVE);
1049 if (sc->vge_irq == NULL) {
1056 vge_reset(sc);
1058 CSR_WRITE_1(sc, VGE_EECSR, VGE_EECSR_RELOAD);
1061 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0)
1071 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI);
1076 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0);
1083 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0)
1084 sc->vge_phyaddr = 1;
1086 sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) &
1089 vge_clrwol(sc);
1090 vge_sysctl_node(sc);
1091 error = vge_dma_alloc(sc);
1095 ifp = sc->vge_ifp = if_alloc(IFT_ETHER);
1102 vge_miipoll_start(sc);
1104 error = mii_attach(dev, &sc->vge_miibus, ifp, vge_ifmedia_upd,
1105 vge_ifmedia_sts, BMSR_DEFCAPMASK, sc->vge_phyaddr, MII_OFFSET_ANY,
1112 if_setsoftc(ifp, sc);
1121 if ((sc->vge_flags & VGE_FLAG_PMCAP) != 0)
1140 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE,
1141 NULL, vge_intr, sc, &sc->vge_intrhand);
1166 struct vge_softc *sc;
1169 sc = device_get_softc(dev);
1170 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized"));
1171 ifp = sc->vge_ifp;
1181 VGE_LOCK(sc);
1182 vge_stop(sc);
1183 VGE_UNLOCK(sc);
1184 callout_drain(&sc->vge_watchdog);
1186 if (sc->vge_miibus)
1187 device_delete_child(dev, sc->vge_miibus);
1190 if (sc->vge_intrhand)
1191 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand);
1192 if (sc->vge_irq)
1194 sc->vge_flags & VGE_FLAG_MSI ? 1 : 0, sc->vge_irq);
1195 if (sc->vge_flags & VGE_FLAG_MSI)
1197 if (sc->vge_res)
1199 PCIR_BAR(1), sc->vge_res);
1203 vge_dma_free(sc);
1204 mtx_destroy(&sc->vge_mtx);
1210 vge_discard_rxbuf(struct vge_softc *sc, int prod)
1215 rxd = &sc->vge_cdata.vge_rxdesc[prod];
1232 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK;
1237 vge_newbuf(struct vge_softc *sc, int prod)
1261 if (bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_rx_tag,
1262 sc->vge_cdata.vge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1268 rxd = &sc->vge_cdata.vge_rxdesc[prod];
1270 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap,
1272 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap);
1275 rxd->rx_dmamap = sc->vge_cdata.vge_rx_sparemap;
1276 sc->vge_cdata.vge_rx_sparemap = map;
1277 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap,
1300 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK;
1307 vge_tx_list_init(struct vge_softc *sc)
1313 VGE_LOCK_ASSERT(sc);
1315 sc->vge_cdata.vge_tx_prodidx = 0;
1316 sc->vge_cdata.vge_tx_considx = 0;
1317 sc->vge_cdata.vge_tx_cnt = 0;
1319 rd = &sc->vge_rdata;
1322 txd = &sc->vge_cdata.vge_txdesc[i];
1327 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag,
1328 sc->vge_cdata.vge_tx_ring_map,
1335 vge_rx_list_init(struct vge_softc *sc)
1341 VGE_LOCK_ASSERT(sc);
1343 sc->vge_cdata.vge_rx_prodidx = 0;
1344 sc->vge_cdata.vge_head = NULL;
1345 sc->vge_cdata.vge_tail = NULL;
1346 sc->vge_cdata.vge_rx_commit = 0;
1348 rd = &sc->vge_rdata;
1351 rxd = &sc->vge_cdata.vge_rxdesc[i];
1356 &sc->vge_cdata.vge_rxdesc[VGE_RX_DESC_CNT - 1];
1358 rxd->rxd_prev = &sc->vge_cdata.vge_rxdesc[i - 1];
1359 if (vge_newbuf(sc, i) != 0)
1363 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag,
1364 sc->vge_cdata.vge_rx_ring_map,
1367 sc->vge_cdata.vge_rx_commit = 0;
1373 vge_freebufs(struct vge_softc *sc)
1380 VGE_LOCK_ASSERT(sc);
1382 ifp = sc->vge_ifp;
1387 rxd = &sc->vge_cdata.vge_rxdesc[i];
1389 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag,
1391 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag,
1399 txd = &sc->vge_cdata.vge_txdesc[i];
1401 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag,
1403 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag,
1434 vge_rxeof(struct vge_softc *sc, int count)
1443 VGE_LOCK_ASSERT(sc);
1445 ifp = sc->vge_ifp;
1447 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag,
1448 sc->vge_cdata.vge_rx_ring_map,
1451 prod = sc->vge_cdata.vge_rx_prodidx;
1455 cur_rx = &sc->vge_rdata.vge_rx_ring[prod];
1463 rxd = &sc->vge_cdata.vge_rxdesc[prod];
1473 if (vge_newbuf(sc, prod) != 0) {
1475 VGE_CHAIN_RESET(sc);
1476 vge_discard_rxbuf(sc, prod);
1480 if (sc->vge_cdata.vge_head == NULL) {
1481 sc->vge_cdata.vge_head = m;
1482 sc->vge_cdata.vge_tail = m;
1485 sc->vge_cdata.vge_tail->m_next = m;
1486 sc->vge_cdata.vge_tail = m;
1510 VGE_CHAIN_RESET(sc);
1511 vge_discard_rxbuf(sc, prod);
1515 if (vge_newbuf(sc, prod) != 0) {
1517 VGE_CHAIN_RESET(sc);
1518 vge_discard_rxbuf(sc, prod);
1523 if (sc->vge_cdata.vge_head != NULL) {
1532 sc->vge_cdata.vge_tail->m_len -=
1538 sc->vge_cdata.vge_tail->m_next = m;
1540 m = sc->vge_cdata.vge_head;
1583 VGE_UNLOCK(sc);
1585 VGE_LOCK(sc);
1586 sc->vge_cdata.vge_head = NULL;
1587 sc->vge_cdata.vge_tail = NULL;
1591 sc->vge_cdata.vge_rx_prodidx = prod;
1592 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag,
1593 sc->vge_cdata.vge_rx_ring_map,
1596 if (sc->vge_cdata.vge_rx_commit != 0) {
1597 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT,
1598 sc->vge_cdata.vge_rx_commit);
1599 sc->vge_cdata.vge_rx_commit = 0;
1606 vge_txeof(struct vge_softc *sc)
1614 VGE_LOCK_ASSERT(sc);
1616 ifp = sc->vge_ifp;
1618 if (sc->vge_cdata.vge_tx_cnt == 0)
1621 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag,
1622 sc->vge_cdata.vge_tx_ring_map,
1629 cons = sc->vge_cdata.vge_tx_considx;
1630 prod = sc->vge_cdata.vge_tx_prodidx;
1632 cur_tx = &sc->vge_rdata.vge_tx_ring[cons];
1636 sc->vge_cdata.vge_tx_cnt--;
1639 txd = &sc->vge_cdata.vge_txdesc[cons];
1640 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap,
1642 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap);
1650 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag,
1651 sc->vge_cdata.vge_tx_ring_map,
1653 sc->vge_cdata.vge_tx_considx = cons;
1654 if (sc->vge_cdata.vge_tx_cnt == 0)
1655 sc->vge_timer = 0;
1661 struct vge_softc *sc;
1665 sc = xsc;
1666 ifp = sc->vge_ifp;
1667 VGE_LOCK_ASSERT(sc);
1669 physts = CSR_READ_1(sc, VGE_PHYSTS0);
1672 sc->vge_flags &= ~VGE_FLAG_LINK;
1673 if_link_state_change(sc->vge_ifp,
1676 sc->vge_flags |= VGE_FLAG_LINK;
1677 if_link_state_change(sc->vge_ifp,
1679 CSR_WRITE_1(sc, VGE_CRC2, VGE_CR2_FDX_TXFLOWCTL_ENABLE |
1683 CSR_WRITE_1(sc, VGE_CRS2,
1686 CSR_WRITE_1(sc, VGE_CRS2,
1697 vge_miipoll_start(sc);
1704 struct vge_softc *sc = if_getsoftc(ifp);
1707 VGE_LOCK(sc);
1711 rx_npkts = vge_rxeof(sc, count);
1712 vge_txeof(sc);
1719 status = CSR_READ_4(sc, VGE_ISR);
1723 CSR_WRITE_4(sc, VGE_ISR, status);
1732 vge_init_locked(sc);
1736 vge_rxeof(sc, count);
1737 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1738 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1742 VGE_UNLOCK(sc);
1750 struct vge_softc *sc;
1754 sc = arg;
1755 VGE_LOCK(sc);
1757 ifp = sc->vge_ifp;
1758 if ((sc->vge_flags & VGE_FLAG_SUSPENDED) != 0 ||
1760 VGE_UNLOCK(sc);
1766 status = CSR_READ_4(sc, VGE_ISR);
1767 CSR_WRITE_4(sc, VGE_ISR, status);
1769 vge_link_statchg(sc);
1770 VGE_UNLOCK(sc);
1776 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1777 status = CSR_READ_4(sc, VGE_ISR);
1778 CSR_WRITE_4(sc, VGE_ISR, status | VGE_ISR_HOLDOFF_RELOAD);
1784 vge_rxeof(sc, VGE_RX_DESC_CNT);
1786 vge_rxeof(sc, VGE_RX_DESC_CNT);
1787 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1788 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1792 vge_txeof(sc);
1796 vge_init_locked(sc);
1800 vge_link_statchg(sc);
1805 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1810 VGE_UNLOCK(sc);
1814 vge_encap(struct vge_softc *sc, struct mbuf **m_head)
1823 VGE_LOCK_ASSERT(sc);
1859 txd = &sc->vge_cdata.vge_txdesc[sc->vge_cdata.vge_tx_prodidx];
1861 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag,
1871 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag,
1880 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap,
1922 sc->vge_cdata.vge_tx_cnt++;
1923 VGE_TX_DESC_INC(sc->vge_cdata.vge_tx_prodidx);
1943 struct vge_softc *sc;
1945 sc = if_getsoftc(ifp);
1946 VGE_LOCK(sc);
1948 VGE_UNLOCK(sc);
1954 struct vge_softc *sc;
1959 sc = if_getsoftc(ifp);
1961 VGE_LOCK_ASSERT(sc);
1963 if ((sc->vge_flags & VGE_FLAG_LINK) == 0 ||
1968 idx = sc->vge_cdata.vge_tx_prodidx;
1971 sc->vge_cdata.vge_tx_cnt < VGE_TX_DESC_CNT - 1; ) {
1980 if (vge_encap(sc, &m_head)) {
1988 txd = &sc->vge_cdata.vge_txdesc[idx];
2001 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag,
2002 sc->vge_cdata.vge_tx_ring_map,
2005 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0);
2009 sc->vge_timer = 5;
2016 struct vge_softc *sc = xsc;
2018 VGE_LOCK(sc);
2019 vge_init_locked(sc);
2020 VGE_UNLOCK(sc);
2024 vge_init_locked(struct vge_softc *sc)
2026 if_t ifp = sc->vge_ifp;
2029 VGE_LOCK_ASSERT(sc);
2037 vge_stop(sc);
2038 vge_reset(sc);
2039 vge_miipoll_start(sc);
2045 error = vge_rx_list_init(sc);
2047 device_printf(sc->vge_dev, "no memory for Rx buffers.\n");
2050 vge_tx_list_init(sc);
2052 vge_stats_clear(sc);
2055 CSR_WRITE_1(sc, VGE_PAR0 + i, if_getlladdr(sc->vge_ifp)[i]);
2061 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT);
2062 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES);
2065 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN);
2066 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128);
2068 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK);
2071 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM|
2073 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET);
2076 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS);
2083 CSR_WRITE_4(sc, VGE_TXDESC_HIADDR,
2084 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr));
2085 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0,
2086 VGE_ADDR_LO(sc->vge_rdata.vge_tx_ring_paddr));
2087 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1);
2089 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO,
2090 VGE_ADDR_LO(sc->vge_rdata.vge_rx_ring_paddr));
2091 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1);
2092 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT);
2095 vge_intr_holdoff(sc);
2098 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
2099 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
2102 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0);
2105 vge_cam_clear(sc);
2108 vge_rxfilter(sc);
2109 vge_setvlan(sc);
2112 CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF);
2119 CSR_WRITE_1(sc, VGE_CRC2, 0xFF);
2120 CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_XON_ENABLE | 0x0B);
2125 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP);
2126 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL);
2127 CSR_WRITE_1(sc, VGE_CRS0,
2135 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS_POLLING);
2142 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS);
2144 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
2145 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
2147 sc->vge_flags &= ~VGE_FLAG_LINK;
2148 vge_ifmedia_upd_locked(sc);
2152 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc);
2161 struct vge_softc *sc;
2164 sc = if_getsoftc(ifp);
2165 VGE_LOCK(sc);
2166 error = vge_ifmedia_upd_locked(sc);
2167 VGE_UNLOCK(sc);
2173 vge_ifmedia_upd_locked(struct vge_softc *sc)
2179 mii = device_get_softc(sc->vge_miibus);
2182 vge_setmedia(sc);
2194 struct vge_softc *sc;
2197 sc = if_getsoftc(ifp);
2198 mii = device_get_softc(sc->vge_miibus);
2200 VGE_LOCK(sc);
2202 VGE_UNLOCK(sc);
2208 VGE_UNLOCK(sc);
2212 vge_setmedia(struct vge_softc *sc)
2217 mii = device_get_softc(sc->vge_miibus);
2233 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2234 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2237 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2238 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2242 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2244 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2246 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2250 device_printf(sc->vge_dev, "unknown media type: %x\n",
2259 struct vge_softc *sc = if_getsoftc(ifp);
2266 VGE_LOCK(sc);
2271 (sc->vge_flags & VGE_FLAG_JUMBO) == 0)
2276 VGE_UNLOCK(sc);
2279 VGE_LOCK(sc);
2282 ((if_getflags(ifp) ^ sc->vge_if_flags) &
2284 vge_rxfilter(sc);
2286 vge_init_locked(sc);
2288 vge_stop(sc);
2289 sc->vge_if_flags = if_getflags(ifp);
2290 VGE_UNLOCK(sc);
2294 VGE_LOCK(sc);
2296 vge_rxfilter(sc);
2297 VGE_UNLOCK(sc);
2301 mii = device_get_softc(sc->vge_miibus);
2312 VGE_LOCK(sc);
2314 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS_POLLING);
2315 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
2316 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
2318 VGE_UNLOCK(sc);
2322 VGE_LOCK(sc);
2323 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS);
2324 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
2325 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
2327 VGE_UNLOCK(sc);
2331 VGE_LOCK(sc);
2358 vge_setvlan(sc);
2360 VGE_UNLOCK(sc);
2374 struct vge_softc *sc;
2377 sc = arg;
2378 VGE_LOCK_ASSERT(sc);
2379 vge_stats_update(sc);
2380 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc);
2381 if (sc->vge_timer == 0 || --sc->vge_timer > 0)
2384 ifp = sc->vge_ifp;
2388 vge_txeof(sc);
2389 vge_rxeof(sc, VGE_RX_DESC_CNT);
2392 vge_init_locked(sc);
2400 vge_stop(struct vge_softc *sc)
2404 VGE_LOCK_ASSERT(sc);
2405 ifp = sc->vge_ifp;
2406 sc->vge_timer = 0;
2407 callout_stop(&sc->vge_watchdog);
2411 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
2412 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP);
2413 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
2414 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF);
2415 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF);
2416 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0);
2418 vge_stats_update(sc);
2419 VGE_CHAIN_RESET(sc);
2420 vge_txeof(sc);
2421 vge_freebufs(sc);
2432 struct vge_softc *sc;
2434 sc = device_get_softc(dev);
2436 VGE_LOCK(sc);
2437 vge_stop(sc);
2438 vge_setwol(sc);
2439 sc->vge_flags |= VGE_FLAG_SUSPENDED;
2440 VGE_UNLOCK(sc);
2453 struct vge_softc *sc;
2457 sc = device_get_softc(dev);
2458 VGE_LOCK(sc);
2459 if ((sc->vge_flags & VGE_FLAG_PMCAP) != 0) {
2461 pmstat = pci_read_config(sc->vge_dev,
2462 sc->vge_pmcap + PCIR_POWER_STATUS, 2);
2465 pci_write_config(sc->vge_dev,
2466 sc->vge_pmcap + PCIR_POWER_STATUS, pmstat, 2);
2469 vge_clrwol(sc);
2471 vge_miipoll_start(sc);
2472 ifp = sc->vge_ifp;
2476 vge_init_locked(sc);
2478 sc->vge_flags &= ~VGE_FLAG_SUSPENDED;
2479 VGE_UNLOCK(sc);
2499 vge_sysctl_node(struct vge_softc *sc)
2506 stats = &sc->vge_stats;
2507 ctx = device_get_sysctl_ctx(sc->vge_dev);
2508 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vge_dev));
2511 CTLFLAG_RW, &sc->vge_int_holdoff, 0, "interrupt holdoff");
2513 CTLFLAG_RW, &sc->vge_rx_coal_pkt, 0, "rx coalescing packet");
2515 CTLFLAG_RW, &sc->vge_tx_coal_pkt, 0, "tx coalescing packet");
2518 sc->vge_int_holdoff = VGE_INT_HOLDOFF_DEFAULT;
2519 resource_int_value(device_get_name(sc->vge_dev),
2520 device_get_unit(sc->vge_dev), "int_holdoff", &sc->vge_int_holdoff);
2521 sc->vge_rx_coal_pkt = VGE_RX_COAL_PKT_DEFAULT;
2522 resource_int_value(device_get_name(sc->vge_dev),
2523 device_get_unit(sc->vge_dev), "rx_coal_pkt", &sc->vge_rx_coal_pkt);
2524 sc->vge_tx_coal_pkt = VGE_TX_COAL_PKT_DEFAULT;
2525 resource_int_value(device_get_name(sc->vge_dev),
2526 device_get_unit(sc->vge_dev), "tx_coal_pkt", &sc->vge_tx_coal_pkt);
2608 vge_stats_clear(sc);
2614 vge_stats_clear(struct vge_softc *sc)
2618 CSR_WRITE_1(sc, VGE_MIBCSR,
2619 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FREEZE);
2620 CSR_WRITE_1(sc, VGE_MIBCSR,
2621 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_CLR);
2624 if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_CLR) == 0)
2628 device_printf(sc->vge_dev, "MIB clear timed out!\n");
2629 CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) &
2634 vge_stats_update(struct vge_softc *sc)
2641 VGE_LOCK_ASSERT(sc);
2643 stats = &sc->vge_stats;
2644 ifp = sc->vge_ifp;
2646 CSR_WRITE_1(sc, VGE_MIBCSR,
2647 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FLUSH);
2650 if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_FLUSH) == 0)
2654 device_printf(sc->vge_dev, "MIB counter dump timed out!\n");
2655 vge_stats_clear(sc);
2662 CSR_WRITE_1(sc, VGE_MIBCSR,
2663 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_RINI);
2665 val = CSR_READ_4(sc, VGE_MIBDATA);
2734 vge_intr_holdoff(struct vge_softc *sc)
2738 VGE_LOCK_ASSERT(sc);
2751 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_TXSUPPTHR);
2752 CSR_WRITE_1(sc, VGE_TXSUPPTHR, sc->vge_tx_coal_pkt);
2755 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR);
2756 CSR_WRITE_1(sc, VGE_RXSUPPTHR, sc->vge_rx_coal_pkt);
2758 intctl = CSR_READ_1(sc, VGE_INTCTL1);
2761 if (sc->vge_tx_coal_pkt <= 0)
2765 if (sc->vge_rx_coal_pkt <= 0)
2769 CSR_WRITE_1(sc, VGE_INTCTL1, intctl);
2770 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_HOLDOFF);
2771 if (sc->vge_int_holdoff > 0) {
2773 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF);
2774 CSR_WRITE_1(sc, VGE_INTHOLDOFF,
2775 VGE_INT_HOLDOFF_USEC(sc->vge_int_holdoff));
2777 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF);
2782 vge_setlinkspeed(struct vge_softc *sc)
2787 VGE_LOCK_ASSERT(sc);
2789 mii = device_get_softc(sc->vge_miibus);
2805 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2806 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2807 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_100T2CR, 0);
2808 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_ANAR,
2810 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR,
2827 VGE_UNLOCK(sc);
2829 VGE_LOCK(sc);
2832 device_printf(sc->vge_dev, "establishing link failed, "
2844 vge_setwol(struct vge_softc *sc)
2850 VGE_LOCK_ASSERT(sc);
2852 if ((sc->vge_flags & VGE_FLAG_PMCAP) == 0) {
2854 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR,
2856 vge_miipoll_stop(sc);
2860 ifp = sc->vge_ifp;
2863 CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL);
2865 CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F);
2866 CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM |
2869 vge_setlinkspeed(sc);
2875 CSR_WRITE_1(sc, VGE_WOLCR1S, val);
2879 CSR_WRITE_1(sc, VGE_WOLCFGS, val | VGE_WOLCFG_PMEOVR);
2881 vge_miipoll_stop(sc);
2883 CSR_SETBIT_1(sc, VGE_DIAGCTL,
2885 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII);
2888 CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF);
2889 CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF);
2891 val = CSR_READ_1(sc, VGE_PWRSTAT);
2893 CSR_WRITE_1(sc, VGE_PWRSTAT, val);
2895 val = CSR_READ_1(sc, VGE_PWRSTAT);
2897 CSR_WRITE_1(sc, VGE_PWRSTAT, val);
2899 pmstat = pci_read_config(sc->vge_dev, sc->vge_pmcap +
2904 pci_write_config(sc->vge_dev, sc->vge_pmcap + PCIR_POWER_STATUS,
2909 vge_clrwol(struct vge_softc *sc)
2913 val = CSR_READ_1(sc, VGE_PWRSTAT);
2915 CSR_WRITE_1(sc, VGE_PWRSTAT, val);
2917 val = CSR_READ_1(sc, VGE_PWRSTAT);
2919 CSR_WRITE_1(sc, VGE_PWRSTAT, val);
2921 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII);
2922 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2925 CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL);
2927 CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F);
2928 CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM |
2931 CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF);
2932 CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF);