Lines Matching refs:sc
65 qcom_spi_hw_read_controller_transfer_sizes(struct qcom_spi_softc *sc)
69 reg = QCOM_SPI_READ_4(sc, QUP_IO_M_MODES);
71 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TRANSFER_SETUP,
78 sc->config.input_block_size = 4;
80 sc->config.input_block_size = val * 16;
86 sc->config.output_block_size = 4;
88 sc->config.output_block_size = val * 16;
93 sc->config.input_fifo_size =
94 sc->config.input_block_size * (2 << val);
99 sc->config.output_fifo_size =
100 sc->config.output_block_size * (2 << val);
106 qcom_spi_hw_qup_is_state_valid_locked(struct qcom_spi_softc *sc)
110 QCOM_SPI_ASSERT_LOCKED(sc);
112 reg = QCOM_SPI_READ_4(sc, QUP_STATE);
113 QCOM_SPI_BARRIER_READ(sc);
119 qcom_spi_hw_qup_wait_state_valid_locked(struct qcom_spi_softc *sc)
124 if (qcom_spi_hw_qup_is_state_valid_locked(sc))
128 device_printf(sc->sc_dev,
136 qcom_spi_hw_is_opmode_dma_locked(struct qcom_spi_softc *sc)
139 QCOM_SPI_ASSERT_LOCKED(sc);
141 if (sc->state.transfer_mode == QUP_IO_M_MODE_DMOV)
143 if (sc->state.transfer_mode == QUP_IO_M_MODE_BAM)
149 qcom_spi_hw_qup_set_state_locked(struct qcom_spi_softc *sc, uint32_t state)
154 QCOM_SPI_ASSERT_LOCKED(sc);
157 ret = qcom_spi_hw_qup_wait_state_valid_locked(sc);
162 cur_state = QCOM_SPI_READ_4(sc, QUP_STATE);
164 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_STATE_CHANGE,
174 QCOM_SPI_WRITE_4(sc, QUP_STATE, QUP_STATE_CLEAR);
175 QCOM_SPI_BARRIER_WRITE(sc);
176 QCOM_SPI_WRITE_4(sc, QUP_STATE, QUP_STATE_CLEAR);
177 QCOM_SPI_BARRIER_WRITE(sc);
181 QCOM_SPI_WRITE_4(sc, QUP_STATE, cur_state);
182 QCOM_SPI_BARRIER_WRITE(sc);
186 ret = qcom_spi_hw_qup_wait_state_valid_locked(sc);
191 cur_state = QCOM_SPI_READ_4(sc, QUP_STATE);
193 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_STATE_CHANGE,
207 qcom_spi_hw_qup_init_locked(struct qcom_spi_softc *sc)
211 QCOM_SPI_ASSERT_LOCKED(sc);
214 (void) qcom_spi_hw_do_full_reset(sc);
216 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RESET);
218 device_printf(sc->sc_dev, "ERROR: %s: couldn't reset\n",
223 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL, 0);
224 QCOM_SPI_WRITE_4(sc, QUP_IO_M_MODES, 0);
226 if (! QCOM_SPI_QUP_VERSION_V1(sc))
227 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL_MASK, 0);
230 if (QCOM_SPI_QUP_VERSION_V1(sc))
231 QCOM_SPI_WRITE_4(sc, QUP_ERROR_FLAGS_EN,
235 QCOM_SPI_BARRIER_WRITE(sc);
246 qcom_spi_hw_spi_init_locked(struct qcom_spi_softc *sc)
249 QCOM_SPI_ASSERT_LOCKED(sc);
252 QCOM_SPI_WRITE_4(sc, SPI_ERROR_FLAGS_EN,
255 QCOM_SPI_BARRIER_WRITE(sc);
258 QCOM_SPI_WRITE_4(sc, SPI_CONFIG, 0);
259 QCOM_SPI_BARRIER_WRITE(sc);
262 QCOM_SPI_WRITE_4(sc, SPI_IO_CONTROL,
264 | SPI_IO_C_CS_SELECT(sc->config.cs_select));
265 QCOM_SPI_BARRIER_WRITE(sc);
282 qcom_spi_hw_spi_cs_force(struct qcom_spi_softc *sc, int cs, bool enable)
286 QCOM_SPI_ASSERT_LOCKED(sc);
288 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_CHIPSELECT,
292 reg = QCOM_SPI_READ_4(sc, SPI_IO_CONTROL);
299 QCOM_SPI_WRITE_4(sc, SPI_IO_CONTROL, reg);
300 QCOM_SPI_BARRIER_WRITE(sc);
309 qcom_spi_hw_interrupt_handle(struct qcom_spi_softc *sc)
313 QCOM_SPI_ASSERT_LOCKED(sc);
316 qup_error = QCOM_SPI_READ_4(sc, QUP_ERROR_FLAGS);
317 spi_error = QCOM_SPI_READ_4(sc, SPI_ERROR_FLAGS);
318 op_flags = QCOM_SPI_READ_4(sc, QUP_OPERATIONAL);
321 QCOM_SPI_WRITE_4(sc, QUP_ERROR_FLAGS, qup_error);
322 QCOM_SPI_WRITE_4(sc, SPI_ERROR_FLAGS, spi_error);
324 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_INTR,
333 device_printf(sc->sc_dev, "ERROR: (QUP) mask=0x%08x\n",
335 sc->intr.error = true;
338 device_printf(sc->sc_dev, "ERROR: (SPI) mask=0x%08x\n",
340 sc->intr.error = true;
344 if (qcom_spi_hw_is_opmode_dma_locked(sc)) {
346 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL, op_flags);
349 sc->intr.rx_dma_done = true;
352 sc->intr.tx_dma_done = true;
356 sc->intr.do_rx = true;
358 sc->intr.do_tx = true;
363 sc->intr.done = true;
364 if (sc->intr.error)
365 sc->intr.done = true;
378 qcom_spi_hw_setup_transfer_selection(struct qcom_spi_softc *sc, uint32_t len)
381 QCOM_SPI_ASSERT_LOCKED(sc);
387 sc->state.transfer_mode = QUP_IO_M_MODE_FIFO;
388 sc->transfer.tx_offset = 0;
389 sc->transfer.rx_offset = 0;
390 sc->transfer.tx_len = 0;
391 sc->transfer.rx_len = 0;
392 sc->transfer.tx_buf = NULL;
393 sc->transfer.rx_buf = NULL;
403 sc->state.transfer_word_size = 4;
405 sc->state.transfer_word_size = 1;
414 qcom_spi_hw_complete_transfer(struct qcom_spi_softc *sc)
416 QCOM_SPI_ASSERT_LOCKED(sc);
418 sc->state.transfer_mode = QUP_IO_M_MODE_FIFO;
419 sc->transfer.tx_offset = 0;
420 sc->transfer.rx_offset = 0;
421 sc->transfer.tx_len = 0;
422 sc->transfer.rx_len = 0;
423 sc->transfer.tx_buf = NULL;
424 sc->transfer.rx_buf = NULL;
425 sc->state.transfer_word_size = 0;
436 qcom_spi_hw_setup_current_transfer(struct qcom_spi_softc *sc)
440 QCOM_SPI_ASSERT_LOCKED(sc);
449 bytes_left = sc->transfer.tx_len - sc->transfer.tx_offset;
451 if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO) {
458 sc->transfer.num_words = bytes_left / sc->state.transfer_word_size;
459 sc->transfer.num_words = MIN(sc->transfer.num_words,
460 sc->config.input_fifo_size / sizeof(uint32_t));
461 } else if (sc->state.transfer_mode == QUP_IO_M_MODE_BLOCK) {
471 sc->transfer.num_words = bytes_left / sc->state.transfer_word_size;
472 sc->transfer.num_words = MIN(sc->transfer.num_words,
477 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TRANSFER_SETUP,
483 sc->transfer.tx_len,
484 sc->transfer.tx_offset,
485 sc->state.transfer_word_size,
487 sc->transfer.num_words,
488 sc->config.input_fifo_size / sizeof(uint32_t));
500 qcom_spi_hw_setup_pio_transfer_cnt(struct qcom_spi_softc *sc)
503 QCOM_SPI_ASSERT_LOCKED(sc);
505 QCOM_SPI_WRITE_4(sc, QUP_MX_READ_CNT, sc->transfer.num_words);
506 QCOM_SPI_WRITE_4(sc, QUP_MX_WRITE_CNT, sc->transfer.num_words);
507 QCOM_SPI_WRITE_4(sc, QUP_MX_INPUT_CNT, 0);
508 QCOM_SPI_WRITE_4(sc, QUP_MX_OUTPUT_CNT, 0);
510 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TRANSFER_SETUP,
512 sc->transfer.num_words);
514 QCOM_SPI_BARRIER_WRITE(sc);
527 qcom_spi_hw_setup_block_transfer_cnt(struct qcom_spi_softc *sc)
530 QCOM_SPI_ASSERT_LOCKED(sc);
532 QCOM_SPI_WRITE_4(sc, QUP_MX_READ_CNT, 0);
533 QCOM_SPI_WRITE_4(sc, QUP_MX_WRITE_CNT, 0);
534 QCOM_SPI_WRITE_4(sc, QUP_MX_INPUT_CNT, sc->transfer.num_words);
535 QCOM_SPI_WRITE_4(sc, QUP_MX_OUTPUT_CNT, sc->transfer.num_words);
536 QCOM_SPI_BARRIER_WRITE(sc);
542 qcom_spi_hw_setup_io_modes(struct qcom_spi_softc *sc)
546 QCOM_SPI_ASSERT_LOCKED(sc);
548 reg = QCOM_SPI_READ_4(sc, QUP_IO_M_MODES);
561 if (qcom_spi_hw_is_opmode_dma_locked(sc))
567 reg |= ((sc->state.transfer_mode & QUP_IO_M_INPUT_MODE_MASK)
569 reg |= ((sc->state.transfer_mode & QUP_IO_M_OUTPUT_MODE_MASK)
572 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TRANSFER_SETUP,
575 QCOM_SPI_WRITE_4(sc, QUP_IO_M_MODES, reg);
576 QCOM_SPI_BARRIER_WRITE(sc);
582 qcom_spi_hw_setup_spi_io_clock_polarity(struct qcom_spi_softc *sc,
587 QCOM_SPI_ASSERT_LOCKED(sc);
589 reg = QCOM_SPI_READ_4(sc, SPI_IO_CONTROL);
596 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TRANSFER_SETUP,
599 QCOM_SPI_WRITE_4(sc, SPI_IO_CONTROL, reg);
600 QCOM_SPI_BARRIER_WRITE(sc);
606 qcom_spi_hw_setup_spi_config(struct qcom_spi_softc *sc, uint32_t clock_val,
617 QCOM_SPI_ASSERT_LOCKED(sc);
619 reg = QCOM_SPI_READ_4(sc, SPI_CONFIG);
638 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TRANSFER_SETUP,
641 QCOM_SPI_WRITE_4(sc, SPI_CONFIG, reg);
642 QCOM_SPI_BARRIER_WRITE(sc);
648 qcom_spi_hw_setup_qup_config(struct qcom_spi_softc *sc, bool is_tx, bool is_rx)
652 QCOM_SPI_ASSERT_LOCKED(sc);
654 reg = QCOM_SPI_READ_4(sc, QUP_CONFIG);
661 reg |= ((sc->state.transfer_word_size * 8) - 1) & QUP_CONFIG_N;
668 if (qcom_spi_hw_is_opmode_dma_locked(sc)) {
675 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TRANSFER_SETUP,
678 QCOM_SPI_WRITE_4(sc, QUP_CONFIG, reg);
679 QCOM_SPI_BARRIER_WRITE(sc);
685 qcom_spi_hw_setup_operational_mask(struct qcom_spi_softc *sc)
688 QCOM_SPI_ASSERT_LOCKED(sc);
690 if (QCOM_SPI_QUP_VERSION_V1(sc)) {
691 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TRANSFER_SETUP,
696 if (qcom_spi_hw_is_opmode_dma_locked(sc))
697 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL_MASK,
700 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL_MASK, 0);
702 QCOM_SPI_BARRIER_WRITE(sc);
711 qcom_spi_hw_ack_write_pio_fifo(struct qcom_spi_softc *sc)
714 QCOM_SPI_ASSERT_LOCKED(sc);
715 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL, QUP_OP_OUT_SERVICE_FLAG);
716 QCOM_SPI_BARRIER_WRITE(sc);
721 qcom_spi_hw_ack_opmode(struct qcom_spi_softc *sc)
724 QCOM_SPI_ASSERT_LOCKED(sc);
726 QCOM_SPI_BARRIER_READ(sc);
727 QCOM_SPI_READ_4(sc, QUP_OPERATIONAL);
728 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL, QUP_OP_OUT_SERVICE_FLAG);
729 QCOM_SPI_BARRIER_WRITE(sc);
742 qcom_spi_hw_write_from_tx_buf(struct qcom_spi_softc *sc, int shift,
746 QCOM_SPI_ASSERT_LOCKED(sc);
748 if (sc->transfer.tx_buf == NULL)
751 if (sc->transfer.tx_offset < sc->transfer.tx_len) {
752 *val |= (sc->transfer.tx_buf[sc->transfer.tx_offset] & 0xff)
754 sc->transfer.tx_offset++;
762 qcom_spi_hw_write_pio_fifo(struct qcom_spi_softc *sc)
767 QCOM_SPI_ASSERT_LOCKED(sc);
769 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL, QUP_OP_OUT_SERVICE_FLAG);
770 QCOM_SPI_BARRIER_WRITE(sc);
775 for (i = 0; i < sc->transfer.num_words; i++) {
779 if ((QCOM_SPI_READ_4(sc, QUP_OPERATIONAL)
781 device_printf(sc->sc_dev, "%s: FIFO full\n", __func__);
798 if (sc->state.transfer_word_size == 1) {
799 if (qcom_spi_hw_write_from_tx_buf(sc, 24, ®))
801 } else if (sc->state.transfer_word_size == 2) {
802 if (qcom_spi_hw_write_from_tx_buf(sc, 24, ®))
804 if (qcom_spi_hw_write_from_tx_buf(sc, 16, ®))
806 } else if (sc->state.transfer_word_size == 4) {
807 if (qcom_spi_hw_write_from_tx_buf(sc, 24, ®))
809 if (qcom_spi_hw_write_from_tx_buf(sc, 16, ®))
811 if (qcom_spi_hw_write_from_tx_buf(sc, 8, ®))
813 if (qcom_spi_hw_write_from_tx_buf(sc, 0, ®))
822 QCOM_SPI_WRITE_4(sc, QUP_OUTPUT_FIFO, reg);
823 QCOM_SPI_BARRIER_WRITE(sc);
826 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TX_FIFO,
828 __func__, num_bytes, sc->transfer.num_words);
834 qcom_spi_hw_write_pio_block(struct qcom_spi_softc *sc)
847 qcom_spi_hw_read_into_rx_buf(struct qcom_spi_softc *sc, uint8_t val)
849 QCOM_SPI_ASSERT_LOCKED(sc);
851 if (sc->transfer.rx_buf == NULL)
855 if (sc->transfer.rx_offset < sc->transfer.rx_len) {
856 sc->transfer.rx_buf[sc->transfer.rx_offset] = val;
857 sc->transfer.rx_offset++;
869 qcom_spi_hw_read_pio_fifo(struct qcom_spi_softc *sc)
875 QCOM_SPI_ASSERT_LOCKED(sc);
877 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL, QUP_OP_IN_SERVICE_FLAG);
878 QCOM_SPI_BARRIER_WRITE(sc);
880 for (i = 0; i < sc->transfer.num_words; i++) {
882 QCOM_SPI_BARRIER_READ(sc);
883 reg = QCOM_SPI_READ_4(sc, QUP_OPERATIONAL);
885 device_printf(sc->sc_dev, "%s: FIFO empty\n", __func__);
894 reg = QCOM_SPI_READ_4(sc, QUP_INPUT_FIFO);
900 if (sc->state.transfer_word_size == 1) {
901 if (qcom_spi_hw_read_into_rx_buf(sc, reg & 0xff))
903 } else if (sc->state.transfer_word_size == 2) {
904 if (qcom_spi_hw_read_into_rx_buf(sc, (reg >> 8) & 0xff))
906 if (qcom_spi_hw_read_into_rx_buf(sc, reg & 0xff))
908 } else if (sc->state.transfer_word_size == 4) {
909 if (qcom_spi_hw_read_into_rx_buf(sc, (reg >> 24) & 0xff))
911 if (qcom_spi_hw_read_into_rx_buf(sc, (reg >> 16) & 0xff))
913 if (qcom_spi_hw_read_into_rx_buf(sc, (reg >> 8) & 0xff))
915 if (qcom_spi_hw_read_into_rx_buf(sc, reg & 0xff))
920 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TX_FIFO,
922 __func__, num_bytes, sc->transfer.num_words);
929 QCOM_SPI_BARRIER_READ(sc);
930 reg = QCOM_SPI_READ_4(sc, QUP_OPERATIONAL);
932 device_printf(sc->sc_dev, "%s: read complete (DONE)\n" ,
934 sc->intr.done = true;
946 if ((sc->state.transfer_mode == QUP_IO_M_MODE_FIFO)
947 && (sc->transfer.rx_offset >= sc->transfer.rx_len)) {
948 device_printf(sc->sc_dev, "%s: read complete (rxlen)\n",
950 sc->intr.done = true;
959 sc->intr.done = true;
965 qcom_spi_hw_read_pio_block(struct qcom_spi_softc *sc)
973 qcom_spi_hw_do_full_reset(struct qcom_spi_softc *sc)
975 QCOM_SPI_ASSERT_LOCKED(sc);
977 QCOM_SPI_WRITE_4(sc, QUP_SW_RESET, 1);
978 QCOM_SPI_BARRIER_WRITE(sc);