Lines Matching refs:sc
157 static void dwmmc_handle_card_present(struct dwmmc_softc *sc, bool is_present);
183 struct dwmmc_softc *sc;
186 sc = arg;
192 sc->desc_ring[idx].des0 = DES0_DIC | DES0_CH;
193 sc->desc_ring[idx].des1 = segs[idx].ds_len & DES1_BS1_MASK;
194 sc->desc_ring[idx].des2 = segs[idx].ds_addr;
197 sc->desc_ring[idx].des0 |= DES0_FS;
200 sc->desc_ring[idx].des0 &= ~(DES0_DIC | DES0_CH);
201 sc->desc_ring[idx].des0 |= DES0_LD;
204 sc->desc_ring[idx].des0 |= DES0_OWN;
209 dwmmc_ctrl_reset(struct dwmmc_softc *sc, int reset_bits)
214 reg = READ4(sc, SDMMC_CTRL);
216 WRITE4(sc, SDMMC_CTRL, reg);
220 if (!(READ4(sc, SDMMC_CTRL) & reset_bits))
225 device_printf(sc->dev, "Reset failed\n");
231 dma_setup(struct dwmmc_softc *sc)
241 bus_get_dma_tag(sc->dev), /* Parent tag. */
250 &sc->desc_tag);
252 device_printf(sc->dev,
257 error = bus_dmamem_alloc(sc->desc_tag, (void**)&sc->desc_ring,
259 &sc->desc_map);
261 device_printf(sc->dev,
266 error = bus_dmamap_load(sc->desc_tag, sc->desc_map,
267 sc->desc_ring, IDMAC_DESC_SIZE, dwmmc_get1paddr,
268 &sc->desc_ring_paddr, 0);
270 device_printf(sc->dev,
276 sc->desc_ring[idx].des0 = DES0_CH;
277 sc->desc_ring[idx].des1 = 0;
279 sc->desc_ring[idx].des3 = sc->desc_ring_paddr + \
282 sc->desc_ring[idx - 1].des3 = sc->desc_ring_paddr;
283 sc->desc_ring[idx - 1].des0 |= DES0_ER;
286 bus_get_dma_tag(sc->dev), /* Parent tag. */
296 &sc->buf_tag);
298 device_printf(sc->dev,
303 error = bus_dmamap_create(sc->buf_tag, 0,
304 &sc->buf_map);
306 device_printf(sc->dev,
315 dwmmc_cmd_done(struct dwmmc_softc *sc)
323 ccb = sc->ccb;
328 cmd = sc->curcmd;
335 cmd->resp[3] = READ4(sc, SDMMC_RESP0);
336 cmd->resp[2] = READ4(sc, SDMMC_RESP1);
337 cmd->resp[1] = READ4(sc, SDMMC_RESP2);
338 cmd->resp[0] = READ4(sc, SDMMC_RESP3);
343 cmd->resp[0] = READ4(sc, SDMMC_RESP0);
349 dwmmc_tasklet(struct dwmmc_softc *sc)
353 cmd = sc->curcmd;
357 if (!sc->cmd_done)
361 dwmmc_next_operation(sc);
362 } else if (cmd->data && sc->dto_rcvd) {
365 sc->use_auto_stop) {
366 if (sc->acd_rcvd)
367 dwmmc_next_operation(sc);
369 dwmmc_next_operation(sc);
378 struct dwmmc_softc *sc;
381 sc = arg;
383 DWMMC_LOCK(sc);
385 cmd = sc->curcmd;
388 reg = READ4(sc, SDMMC_MINTSTS);
402 if (!sc->use_pio) {
403 dma_done(sc, cmd);
404 dma_stop(sc);
409 dwmmc_cmd_done(sc);
410 sc->cmd_done = 1;
414 sc->acd_rcvd = 1;
417 sc->dto_rcvd = 1;
420 dwmmc_handle_card_present(sc,
421 READ4(sc, SDMMC_CDETECT) == 0 ? true : false);
426 WRITE4(sc, SDMMC_RINTSTS, reg);
428 if (sc->use_pio) {
430 pio_read(sc, cmd);
433 pio_write(sc, cmd);
437 reg = READ4(sc, SDMMC_IDSTS);
441 WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI |
443 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI);
444 dma_done(sc, cmd);
449 dwmmc_tasklet(sc);
451 DWMMC_UNLOCK(sc);
455 dwmmc_handle_card_present(struct dwmmc_softc *sc, bool is_present)
462 was_present = sc->child != NULL;
466 &sc->card_delayed_task, -(hz / 2));
468 taskqueue_enqueue(taskqueue_swi_giant, &sc->card_task);
475 struct dwmmc_softc *sc = arg;
478 mmc_cam_sim_discover(&sc->mmc_sim);
480 DWMMC_LOCK(sc);
482 if (READ4(sc, SDMMC_CDETECT) == 0 ||
483 (sc->mmc_helper.props & MMC_PROP_BROKEN_CD)) {
484 if (sc->child == NULL) {
486 device_printf(sc->dev, "Card inserted\n");
488 sc->child = device_add_child(sc->dev, "mmc", -1);
489 DWMMC_UNLOCK(sc);
490 if (sc->child) {
491 device_set_ivars(sc->child, sc);
492 (void)device_probe_and_attach(sc->child);
495 DWMMC_UNLOCK(sc);
498 if (sc->child != NULL) {
500 device_printf(sc->dev, "Card removed\n");
502 DWMMC_UNLOCK(sc);
503 device_delete_child(sc->dev, sc->child);
504 sc->child = NULL;
506 DWMMC_UNLOCK(sc);
512 parse_fdt(struct dwmmc_softc *sc)
520 if ((node = ofw_bus_get_node(sc->dev)) == -1)
524 sc->host.f_min = 400000;
525 sc->host.f_max = 200000000;
526 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
527 sc->host.caps = MMC_CAP_HSPEED | MMC_CAP_SIGNALING_330;
528 mmc_fdt_parse(sc->dev, node, &sc->mmc_helper, &sc->host);
533 sc->fifo_depth = dts_value[0];
537 sc->num_slots = 1;
539 device_printf(sc->dev, "num-slots property is deprecated\n");
541 sc->num_slots = dts_value[0];
551 error = hwreset_get_by_ofw_name(sc->dev, 0, "reset", &sc->hwreset);
555 device_printf(sc->dev, "Cannot get reset\n");
560 error = regulator_get_by_ofw_property(sc->dev, 0, "vmmc-supply",
561 &sc->vmmc);
565 device_printf(sc->dev, "Cannot get regulator 'vmmc-supply'\n");
570 error = regulator_get_by_ofw_property(sc->dev, 0, "vqmmc-supply",
571 &sc->vqmmc);
575 device_printf(sc->dev, "Cannot get regulator 'vqmmc-supply'\n");
580 if (sc->hwreset != NULL) {
581 error = hwreset_assert(sc->hwreset);
583 device_printf(sc->dev, "Cannot assert reset\n");
589 error = clk_get_by_ofw_name(sc->dev, 0, "biu", &sc->biu);
593 device_printf(sc->dev, "Cannot get 'biu' clock\n");
597 if (sc->biu) {
598 error = clk_enable(sc->biu);
600 device_printf(sc->dev, "cannot enable biu clock\n");
609 error = clk_get_by_ofw_name(sc->dev, 0, "ciu", &sc->ciu);
613 device_printf(sc->dev, "Cannot get 'ciu' clock\n");
617 if (sc->ciu) {
619 error = clk_set_freq(sc->ciu, bus_hz, 0);
621 device_printf(sc->dev,
624 error = clk_enable(sc->ciu);
626 device_printf(sc->dev, "cannot enable ciu clock\n");
629 clk_get_freq(sc->ciu, &sc->bus_hz);
633 if (sc->vmmc != NULL) {
634 error = regulator_enable(sc->vmmc);
636 device_printf(sc->dev, "Cannot enable vmmc regulator\n");
640 if (sc->vqmmc != NULL) {
641 error = regulator_enable(sc->vqmmc);
643 device_printf(sc->dev, "Cannot enable vqmmc regulator\n");
649 if (sc->hwreset != NULL) {
650 error = hwreset_deassert(sc->hwreset);
652 device_printf(sc->dev, "Cannot deassert reset\n");
657 if (sc->bus_hz == 0) {
658 device_printf(sc->dev, "No bus speed provided\n");
671 struct dwmmc_softc *sc;
674 sc = device_get_softc(dev);
676 sc->dev = dev;
679 sc->use_auto_stop = 1;
681 error = parse_fdt(sc);
687 DWMMC_LOCK_INIT(sc);
689 if (bus_alloc_resources(dev, dwmmc_spec, sc->res)) {
695 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE,
696 NULL, dwmmc_intr, sc, &sc->intr_cookie);
703 READ4(sc, SDMMC_VERID) & 0xffff);
706 if (dwmmc_ctrl_reset(sc, (SDMMC_CTRL_RESET |
711 dwmmc_setup_bus(sc, sc->host.f_min);
713 if (sc->fifo_depth == 0) {
714 sc->fifo_depth = 1 +
715 ((READ4(sc, SDMMC_FIFOTH) >> SDMMC_FIFOTH_RXWMARK_S) & 0xfff);
717 sc->fifo_depth);
720 if (!sc->use_pio) {
721 dma_stop(sc);
722 if (dma_setup(sc))
726 WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr);
729 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK);
730 WRITE4(sc, SDMMC_IDINTEN, (SDMMC_IDINTEN_NI |
736 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff);
737 WRITE4(sc, SDMMC_INTMASK, 0);
740 WRITE4(sc, SDMMC_TMOUT, 0xffffffff);
743 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff);
744 WRITE4(sc, SDMMC_INTMASK, (SDMMC_INTMASK_CMD_DONE |
751 WRITE4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE);
753 TASK_INIT(&sc->card_task, 0, dwmmc_card_task, sc);
754 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &sc->card_delayed_task, 0,
755 dwmmc_card_task, sc);
758 sc->ccb = NULL;
759 if (mmc_cam_sim_alloc(dev, "dw_mmc", &sc->mmc_sim) != 0) {
769 dwmmc_card_task(sc, 0);
776 struct dwmmc_softc *sc;
779 sc = device_get_softc(dev);
785 taskqueue_drain(taskqueue_swi_giant, &sc->card_task);
786 taskqueue_drain_timeout(taskqueue_swi_giant, &sc->card_delayed_task);
788 if (sc->intr_cookie != NULL) {
789 ret = bus_teardown_intr(dev, sc->res[1], sc->intr_cookie);
793 bus_release_resources(dev, dwmmc_spec, sc->res);
795 DWMMC_LOCK_DESTROY(sc);
797 if (sc->hwreset != NULL && hwreset_deassert(sc->hwreset) != 0)
798 device_printf(sc->dev, "cannot deassert reset\n");
799 if (sc->biu != NULL && clk_disable(sc->biu) != 0)
800 device_printf(sc->dev, "cannot disable biu clock\n");
801 if (sc->ciu != NULL && clk_disable(sc->ciu) != 0)
802 device_printf(sc->dev, "cannot disable ciu clock\n");
804 if (sc->vmmc && regulator_disable(sc->vmmc) != 0)
805 device_printf(sc->dev, "Cannot disable vmmc regulator\n");
806 if (sc->vqmmc && regulator_disable(sc->vqmmc) != 0)
807 device_printf(sc->dev, "Cannot disable vqmmc regulator\n");
810 mmc_cam_sim_free(&sc->mmc_sim);
817 dwmmc_setup_bus(struct dwmmc_softc *sc, int freq)
823 WRITE4(sc, SDMMC_CLKENA, 0);
824 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA |
830 device_printf(sc->dev, "Failed update clk\n");
833 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);
838 WRITE4(sc, SDMMC_CLKENA, 0);
839 WRITE4(sc, SDMMC_CLKSRC, 0);
841 div = (sc->bus_hz != freq) ? DIV_ROUND_UP(sc->bus_hz, 2 * freq) : 0;
843 WRITE4(sc, SDMMC_CLKDIV, div);
844 WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA |
850 device_printf(sc->dev, "Failed to update clk\n");
853 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);
855 WRITE4(sc, SDMMC_CLKENA, (SDMMC_CLKENA_CCLK_EN | SDMMC_CLKENA_LP));
856 WRITE4(sc, SDMMC_CMD, SDMMC_CMD_WAIT_PRVDATA |
862 device_printf(sc->dev, "Failed to enable clk\n");
865 } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);
873 struct dwmmc_softc *sc;
878 sc = device_get_softc(brdev);
879 ios = &sc->host.ios;
888 WRITE4(sc, SDMMC_PWREN, 0);
891 WRITE4(sc, SDMMC_PWREN, 1);
895 mmc_fdt_set_power(&sc->mmc_helper, ios->power_mode);
898 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT);
900 WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT);
902 WRITE4(sc, SDMMC_CTYPE, 0);
904 if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_EXYNOS) {
906 WRITE4(sc, SDMMC_CLKSEL, sc->sdr_timing);
910 reg = READ4(sc, SDMMC_UHS_REG);
917 WRITE4(sc, SDMMC_UHS_REG, reg);
919 if (sc->update_ios)
920 ret = sc->update_ios(sc, ios);
922 dwmmc_setup_bus(sc, ios->clock);
928 dma_done(struct dwmmc_softc *sc, struct mmc_command *cmd)
935 bus_dmamap_sync(sc->buf_tag, sc->buf_map,
938 bus_dmamap_sync(sc->buf_tag, sc->buf_map,
941 bus_dmamap_sync(sc->desc_tag, sc->desc_map,
944 bus_dmamap_unload(sc->buf_tag, sc->buf_map);
950 dma_stop(struct dwmmc_softc *sc)
954 reg = READ4(sc, SDMMC_CTRL);
957 WRITE4(sc, SDMMC_CTRL, reg);
959 reg = READ4(sc, SDMMC_BMOD);
962 WRITE4(sc, SDMMC_BMOD, reg);
968 dma_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd)
976 reg = READ4(sc, SDMMC_INTMASK);
978 WRITE4(sc, SDMMC_INTMASK, reg);
980 err = bus_dmamap_load(sc->buf_tag, sc->buf_map,
982 sc, BUS_DMA_NOWAIT);
987 bus_dmamap_sync(sc->desc_tag, sc->desc_map,
991 bus_dmamap_sync(sc->buf_tag, sc->buf_map,
994 bus_dmamap_sync(sc->buf_tag, sc->buf_map,
998 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S;
999 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S;
1001 WRITE4(sc, SDMMC_FIFOTH, reg);
1004 reg = READ4(sc, SDMMC_CTRL);
1006 WRITE4(sc, SDMMC_CTRL, reg);
1009 reg = READ4(sc, SDMMC_BMOD);
1011 WRITE4(sc, SDMMC_BMOD, reg);
1014 WRITE4(sc, SDMMC_PLDMND, 1);
1020 pio_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd)
1029 reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S;
1030 reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S;
1032 WRITE4(sc, SDMMC_FIFOTH, reg);
1039 pio_read(struct dwmmc_softc *sc, struct mmc_command *cmd)
1055 status = READ4(sc, SDMMC_STATUS);
1058 *p++ = READ4(sc, SDMMC_DATA);
1062 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_RXDR);
1066 pio_write(struct dwmmc_softc *sc, struct mmc_command *cmd)
1082 status = READ4(sc, SDMMC_STATUS);
1085 WRITE4(sc, SDMMC_DATA, *p++);
1089 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_TXDR);
1093 dwmmc_start_cmd(struct dwmmc_softc *sc, struct mmc_command *cmd)
1100 sc->curcmd = cmd;
1105 cmd->mrq = sc->req;
1135 if ((sc->flags & CARD_INIT_DONE) == 0) {
1136 sc->flags |= (CARD_INIT_DONE);
1143 sc->use_auto_stop)
1152 WRITE4(sc, SDMMC_TMOUT, 0xffffffff);
1155 WRITE4(sc, SDMMC_BLKSIZ, cmd->data->block_size);
1156 WRITE4(sc, SDMMC_BYTCNT, cmd->data->len);
1160 WRITE4(sc, SDMMC_BYTCNT, data->len);
1163 WRITE4(sc, SDMMC_BLKSIZ, blksz);
1166 if (sc->use_pio) {
1167 pio_prepare(sc, cmd);
1169 dma_prepare(sc, cmd);
1176 WRITE4(sc, SDMMC_CMDARG, cmd->arg);
1178 WRITE4(sc, SDMMC_CMD, cmdr | SDMMC_CMD_START);
1182 dwmmc_next_operation(struct dwmmc_softc *sc)
1189 ccb = sc->ccb;
1196 req = sc->req;
1202 sc->acd_rcvd = 0;
1203 sc->dto_rcvd = 0;
1204 sc->cmd_done = 0;
1212 while(READ4(sc, SDMMC_STATUS) & (SDMMC_STATUS_DATA_BUSY))
1215 if (sc->flags & PENDING_CMD) {
1216 sc->flags &= ~PENDING_CMD;
1217 dwmmc_start_cmd(sc, cmd);
1219 } else if (sc->flags & PENDING_STOP && !sc->use_auto_stop) {
1220 sc->flags &= ~PENDING_STOP;
1222 //dwmmc_start_cmd(sc, req->stop);
1227 sc->ccb = NULL;
1228 sc->curcmd = NULL;
1233 sc->req = NULL;
1234 sc->curcmd = NULL;
1242 struct dwmmc_softc *sc;
1244 sc = device_get_softc(brdev);
1248 DWMMC_LOCK(sc);
1251 sc->flags |= PENDING_CMD;
1253 if (sc->req != NULL) {
1254 DWMMC_UNLOCK(sc);
1258 sc->req = req;
1259 sc->flags |= PENDING_CMD;
1260 if (sc->req->stop)
1261 sc->flags |= PENDING_STOP;
1263 dwmmc_next_operation(sc);
1265 DWMMC_UNLOCK(sc);
1282 struct dwmmc_softc *sc;
1284 sc = device_get_softc(brdev);
1286 DWMMC_LOCK(sc);
1287 while (sc->bus_busy)
1288 msleep(sc, &sc->sc_mtx, PZERO, "dwmmcah", hz / 5);
1289 sc->bus_busy++;
1290 DWMMC_UNLOCK(sc);
1297 struct dwmmc_softc *sc;
1299 sc = device_get_softc(brdev);
1301 DWMMC_LOCK(sc);
1302 sc->bus_busy--;
1303 wakeup(sc);
1304 DWMMC_UNLOCK(sc);
1312 struct dwmmc_softc *sc;
1314 sc = device_get_softc(bus);
1320 *(int *)result = sc->host.ios.bus_mode;
1323 *(int *)result = sc->host.ios.bus_width;
1326 *(int *)result = sc->host.ios.chip_select;
1329 *(int *)result = sc->host.ios.clock;
1332 *(int *)result = sc->host.f_min;
1335 *(int *)result = sc->host.f_max;
1338 *(int *)result = sc->host.host_ocr;
1341 *(int *)result = sc->host.mode;
1344 *(int *)result = sc->host.ocr;
1347 *(int *)result = sc->host.ios.power_mode;
1350 *(int *)result = sc->host.ios.vdd;
1353 *(int *)result = sc->host.ios.vccq;
1356 *(int *)result = sc->host.caps;
1362 *(int *)result = sc->host.ios.timing;
1371 struct dwmmc_softc *sc;
1373 sc = device_get_softc(bus);
1379 sc->host.ios.bus_mode = value;
1382 sc->host.ios.bus_width = value;
1385 sc->host.ios.chip_select = value;
1388 sc->host.ios.clock = value;
1391 sc->host.mode = value;
1394 sc->host.ocr = value;
1397 sc->host.ios.power_mode = value;
1400 sc->host.ios.vdd = value;
1403 sc->host.ios.timing = value;
1406 sc->host.ios.vccq = value;
1431 struct dwmmc_softc *sc;
1433 sc = device_get_softc(dev);
1435 cts->host_ocr = sc->host.host_ocr;
1436 cts->host_f_min = sc->host.f_min;
1437 cts->host_f_max = sc->host.f_max;
1438 cts->host_caps = sc->host.caps;
1440 memcpy(&cts->ios, &sc->host.ios, sizeof(struct mmc_ios));
1448 struct dwmmc_softc *sc;
1453 sc = device_get_softc(dev);
1454 ios = &sc->host.ios;
1462 device_printf(sc->dev, "Clock => %d\n", ios->clock);
1467 device_printf(sc->dev, "VDD => %d\n", ios->vdd);
1472 device_printf(sc->dev, "CS => %d\n", ios->chip_select);
1477 device_printf(sc->dev, "Bus width => %d\n", ios->bus_width);
1482 device_printf(sc->dev, "Power mode => %d\n", ios->power_mode);
1487 device_printf(sc->dev, "Timing => %d\n", ios->timing);
1492 device_printf(sc->dev, "Bus mode => %d\n", ios->bus_mode);
1497 device_printf(sc->dev, "VCCQ => %d\n", ios->vccq);
1498 res = dwmmc_switch_vccq(sc->dev, NULL);
1499 device_printf(sc->dev, "VCCQ switch result: %d\n", res);
1502 return (dwmmc_update_ios(sc->dev, NULL));
1508 struct dwmmc_softc *sc;
1511 sc = device_get_softc(dev);
1514 DWMMC_LOCK(sc);
1518 device_printf(sc->dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1529 if (sc->ccb != NULL) {
1530 device_printf(sc->dev, "Controller still has an active command\n");
1533 sc->ccb = ccb;
1534 DWMMC_UNLOCK(sc);
1535 dwmmc_request(sc->dev, NULL, NULL);
1543 struct dwmmc_softc *sc;
1545 sc = device_get_softc(dev);
1546 dwmmc_intr(sc);