dev/ixl/i40e_adminq.c

50 		hw->aq.asq.tail = I40E_VF_ATQT1;
51 		hw->aq.asq.head = I40E_VF_ATQH1;
52 		hw->aq.asq.len  = I40E_VF_ATQLEN1;
53 		hw->aq.asq.bal  = I40E_VF_ATQBAL1;
54 		hw->aq.asq.bah  = I40E_VF_ATQBAH1;
61 		hw->aq.asq.tail = I40E_PF_ATQT;
62 		hw->aq.asq.head = I40E_PF_ATQH;
63 		hw->aq.asq.len  = I40E_PF_ATQLEN;
64 		hw->aq.asq.bal  = I40E_PF_ATQBAL;
65 		hw->aq.asq.bah  = I40E_PF_ATQBAH;
82 	ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
90 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
94 		i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
127 	i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
128 	i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
221 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
225 	hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
229 		bi = &hw->aq.asq.r.asq_bi[i];
244 		i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
245 	i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
279 		if (hw->aq.asq.r.asq_bi[i].pa)
280 			i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
283 	i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
286 	i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
289 	i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
304 	wr32(hw, hw->aq.asq.head, 0);
305 	wr32(hw, hw->aq.asq.tail, 0);
309 		wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
312 		wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
314 	wr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa));
315 	wr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa));
318 	reg = rd32(hw, hw->aq.asq.bal);
319 	if (reg != I40E_LO_DWORD(hw->aq.asq.desc_buf.pa))
378 	if (hw->aq.asq.count > 0) {
391 	hw->aq.asq.next_to_use = 0;
392 	hw->aq.asq.next_to_clean = 0;
410 	hw->aq.asq.count = hw->aq.num_asq_entries;
495 	if (hw->aq.asq.count == 0) {
501 	wr32(hw, hw->aq.asq.head, 0);
502 	wr32(hw, hw->aq.asq.tail, 0);
503 	wr32(hw, hw->aq.asq.len, 0);
504 	wr32(hw, hw->aq.asq.bal, 0);
505 	wr32(hw, hw->aq.asq.bah, 0);
507 	hw->aq.asq.count = 0; /* to indicate uninitialized queue */
558 	hw->aq.asq.next_to_use = 0;
559 	hw->aq.asq.next_to_clean = 0;
781 	struct i40e_adminq_ring *asq = &(hw->aq.asq);
783 	u16 ntc = asq->next_to_clean;
787 	desc = I40E_ADMINQ_DESC(*asq, ntc);
788 	details = I40E_ADMINQ_DETAILS(*asq, ntc);
789 	while (rd32(hw, hw->aq.asq.head) != ntc) {
791 			   "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
803 		if (ntc == asq->count)
805 		desc = I40E_ADMINQ_DESC(*asq, ntc);
806 		details = I40E_ADMINQ_DETAILS(*asq, ntc);
809 	asq->next_to_clean = ntc;
811 	return I40E_DESC_UNUSED(asq);
826 	return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
859 	if (hw->aq.asq.count == 0) {
866 	val = rd32(hw, hw->aq.asq.head);
874 	details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
934 	desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
942 		dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
961 	(hw->aq.asq.next_to_use)++;
962 	if (hw->aq.asq.next_to_use == hw->aq.asq.count)
963 		hw->aq.asq.next_to_use = 0;
965 		wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
1023 		if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) {