dev/igc/igc_phy.c

134 	s32 ret_val = IGC_SUCCESS;
142 	ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
143 	if (ret_val)
144 		return ret_val;
148 	ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
149 	if (ret_val)
150 		return ret_val;
289 	s32 ret_val;
299 	ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
300 	if (ret_val)
301 		return ret_val;
305 		ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
307 		if (ret_val)
308 			return ret_val;
313 		ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<
318 		if (ret_val)
319 			return ret_val;
441 	ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
442 	if (ret_val)
443 		return ret_val;
448 		ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
452 		ret_val = phy->ops.write_reg(hw,
458 	return ret_val;
473 	s32 ret_val;
490 	ret_val = igc_phy_setup_autoneg(hw);
491 	if (ret_val) {
493 		return ret_val;
500 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
501 	if (ret_val)
502 		return ret_val;
505 	ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
506 	if (ret_val)
507 		return ret_val;
513 		ret_val = igc_wait_autoneg(hw);
514 		if (ret_val) {
516 			return ret_val;
522 	return ret_val;
536 	s32 ret_val;
545 		ret_val = igc_copper_link_autoneg(hw);
546 		if (ret_val)
547 			return ret_val;
553 		ret_val = hw->phy.ops.force_speed_duplex(hw);
554 		if (ret_val) {
556 			return ret_val;
563 	ret_val = igc_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
565 	if (ret_val)
566 		return ret_val;
571 		ret_val = igc_config_fc_after_link_up_generic(hw);
576 	return ret_val;
657 	s32 ret_val;
665 	ret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data);
666 	if (ret_val)
667 		return ret_val;
671 		ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
673 		if (ret_val)
674 			return ret_val;
681 			ret_val = phy->ops.read_reg(hw,
684 			if (ret_val)
685 				return ret_val;
688 			ret_val = phy->ops.write_reg(hw,
691 			if (ret_val)
692 				return ret_val;
694 			ret_val = phy->ops.read_reg(hw,
697 			if (ret_val)
698 				return ret_val;
701 			ret_val = phy->ops.write_reg(hw,
704 			if (ret_val)
705 				return ret_val;
711 		ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
713 		if (ret_val)
714 			return ret_val;
717 		ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
719 		if (ret_val)
720 			return ret_val;
723 		ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
727 	return ret_val;
741 	s32 ret_val;
753 	return ret_val;
765 	s32 ret_val = IGC_SUCCESS;
775 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
776 		if (ret_val)
778 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
779 		if (ret_val)
789 	return ret_val;
804 	s32 ret_val = IGC_SUCCESS;
817 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
818 		if (ret_val) {
828 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
829 		if (ret_val)
841 	return ret_val;
856 	s32 ret_val;
862 		ret_val = phy->ops.check_reset_block(hw);
863 		if (ret_val)
867 	ret_val = phy->ops.acquire(hw);
868 	if (ret_val)
869 		return ret_val;
895 	return ret_val;
946 	s32 ret_val;
954 		ret_val = hw->phy.ops.acquire(hw);
955 		if (ret_val)
956 			return ret_val;
957 		ret_val = igc_write_phy_reg_mdic(hw, offset, data);
958 		if (ret_val)
959 			return ret_val;
962 		ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr,
965 	return ret_val;
980 	s32 ret_val;
988 		ret_val = hw->phy.ops.acquire(hw);
989 		if (ret_val)
990 			return ret_val;
991 		ret_val = igc_read_phy_reg_mdic(hw, offset, data);
992 		if (ret_val)
993 			return ret_val;
996 		ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr,
999 	return ret_val;
1014 	s32 ret_val;
1018 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);
1019 	if (ret_val)
1020 		return ret_val;
1022 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);
1023 	if (ret_val)
1024 		return ret_val;
1026 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |
1028 	if (ret_val)
1029 		return ret_val;
1032 		ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);
1034 		ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);
1035 	if (ret_val)
1036 		return ret_val;
1039 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);
1040 	if (ret_val)
1041 		return ret_val;
1043 	return ret_val;