etherswitch/mtkswitch/mtkswitch_mt7620.c

57 mtkswitch_phy_read_locked(struct mtkswitch_softc *sc, int phy, int reg)
61 	MTKSWITCH_WRITE(sc, MTKSWITCH_PIAC, PIAC_PHY_ACS_ST | PIAC_MDIO_ST |
64 	while ((data = MTKSWITCH_READ(sc, MTKSWITCH_PIAC)) & PIAC_PHY_ACS_ST);
72 	struct mtkswitch_softc *sc = device_get_softc(dev);
78 	MTKSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
79 	MTKSWITCH_LOCK(sc);
80 	data = mtkswitch_phy_read_locked(sc, phy, reg);
81 	MTKSWITCH_UNLOCK(sc);
87 mtkswitch_phy_write_locked(struct mtkswitch_softc *sc, int phy, int reg,
91 	MTKSWITCH_WRITE(sc, MTKSWITCH_PIAC, PIAC_PHY_ACS_ST | PIAC_MDIO_ST |
94 	while (MTKSWITCH_READ(sc, MTKSWITCH_PIAC) & PIAC_PHY_ACS_ST);
102 	struct mtkswitch_softc *sc = device_get_softc(dev);
108 	MTKSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
109 	MTKSWITCH_LOCK(sc);
110 	res = mtkswitch_phy_write_locked(sc, phy, reg, val);
111 	MTKSWITCH_UNLOCK(sc);
117 mtkswitch_reg_read32(struct mtkswitch_softc *sc, int reg)
120 	return (MTKSWITCH_READ(sc, reg));
124 mtkswitch_reg_write32(struct mtkswitch_softc *sc, int reg, uint32_t val)
127 	MTKSWITCH_WRITE(sc, reg, val);
132 mtkswitch_reg_read32_mt7621(struct mtkswitch_softc *sc, int reg)
136 	mtkswitch_phy_write_locked(sc, MTKSWITCH_GLOBAL_PHY,
138 	low = mtkswitch_phy_read_locked(sc, MTKSWITCH_GLOBAL_PHY,
140 	hi = mtkswitch_phy_read_locked(sc, MTKSWITCH_GLOBAL_PHY,
146 mtkswitch_reg_write32_mt7621(struct mtkswitch_softc *sc, int reg, uint32_t val)
149 	mtkswitch_phy_write_locked(sc, MTKSWITCH_GLOBAL_PHY,
151 	mtkswitch_phy_write_locked(sc, MTKSWITCH_GLOBAL_PHY,
153 	mtkswitch_phy_write_locked(sc, MTKSWITCH_GLOBAL_PHY,
161 	struct mtkswitch_softc *sc = device_get_softc(dev);
164 	val = sc->hal.mtkswitch_read(sc, MTKSWITCH_REG32(reg));
173 	struct mtkswitch_softc *sc = device_get_softc(dev);
176 	tmp = sc->hal.mtkswitch_read(sc, MTKSWITCH_REG32(reg));
184 	sc->hal.mtkswitch_write(sc, MTKSWITCH_REG32(reg), tmp);
190 mtkswitch_reset(struct mtkswitch_softc *sc)
198 mtkswitch_hw_setup(struct mtkswitch_softc *sc)
211 mtkswitch_hw_global_setup(struct mtkswitch_softc *sc)
220 mtkswitch_port_init(struct mtkswitch_softc *sc, int port)
227 	val = sc->hal.mtkswitch_read(sc, MTKSWITCH_PCR(port));
229 	sc->hal.mtkswitch_write(sc, MTKSWITCH_PCR(port), val);
232 	val = sc->hal.mtkswitch_read(sc, MTKSWITCH_PVC(port));
234 	sc->hal.mtkswitch_write(sc, MTKSWITCH_PVC(port), val);
237 	if (port == sc->cpuport)
241 	sc->hal.mtkswitch_write(sc, MTKSWITCH_PMCR(port), val);
245 mtkswitch_get_port_status(struct mtkswitch_softc *sc, int port)
249 	MTKSWITCH_LOCK_ASSERT(sc, MA_OWNED);
251 	val = sc->hal.mtkswitch_read(sc, MTKSWITCH_PMSR(port));
273 mtkswitch_atu_flush(struct mtkswitch_softc *sc)
276 	MTKSWITCH_LOCK_ASSERT(sc, MA_OWNED);
279 	while (sc->hal.mtkswitch_read(sc, MTKSWITCH_ATC) & ATC_BUSY);
280 	sc->hal.mtkswitch_write(sc, MTKSWITCH_ATC, ATC_BUSY |
282 	while (sc->hal.mtkswitch_read(sc, MTKSWITCH_ATC) & ATC_BUSY);
288 mtkswitch_port_vlan_setup(struct mtkswitch_softc *sc, etherswitch_port_t *p)
300 	MTKSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
301 	MTKSWITCH_LOCK(sc);
305 		err = sc->hal.mtkswitch_vlan_set_pvid(sc, p->es_port,
308 			MTKSWITCH_UNLOCK(sc);
313 	MTKSWITCH_UNLOCK(sc);
319 mtkswitch_port_vlan_get(struct mtkswitch_softc *sc, etherswitch_port_t *p)
322 	MTKSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
323 	MTKSWITCH_LOCK(sc);
326 	sc->hal.mtkswitch_vlan_get_pvid(sc, p->es_port, &p->es_pvid);
334 	MTKSWITCH_UNLOCK(sc);
340 mtkswitch_invalidate_vlan(struct mtkswitch_softc *sc, uint32_t vid)
343 	while (sc->hal.mtkswitch_read(sc, MTKSWITCH_VTCR) & VTCR_BUSY);
344 	sc->hal.mtkswitch_write(sc, MTKSWITCH_VTCR, VTCR_BUSY |
346 	while (sc->hal.mtkswitch_read(sc, MTKSWITCH_VTCR) & VTCR_BUSY);
350 mtkswitch_vlan_init_hw(struct mtkswitch_softc *sc)
354 	MTKSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
355 	MTKSWITCH_LOCK(sc);
357 	for (i = 0; i < sc->info.es_nvlangroups; i++) {
358 		mtkswitch_invalidate_vlan(sc, i);
359 		if (sc->sc_switchtype == MTK_SWITCH_MT7620) {
360 			val = sc->hal.mtkswitch_read(sc, MTKSWITCH_VTIM(i));
363 			sc->hal.mtkswitch_write(sc, MTKSWITCH_VTIM(i), val);
368 	if (sc->sc_switchtype == MTK_SWITCH_MT7620) {
376 	for (i = 0; i < sc->info.es_nports; i++)
378 	sc->hal.mtkswitch_write(sc, MTKSWITCH_VAWD1, val);
379 	sc->hal.mtkswitch_write(sc, MTKSWITCH_VAWD2, 0);
381 	sc->hal.mtkswitch_write(sc, MTKSWITCH_VTCR, val);
384 	for (i = 0; i < sc->info.es_nports; i++) {
385 		sc->hal.mtkswitch_vlan_set_pvid(sc, i, 1);
388 	MTKSWITCH_UNLOCK(sc);
392 mtkswitch_vlan_getvgroup(struct mtkswitch_softc *sc, etherswitch_vlangroup_t *v)
396 	MTKSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
398 	if ((sc->vlan_mode != ETHERSWITCH_VLAN_DOT1Q) ||
399 	    (v->es_vlangroup > sc->info.es_nvlangroups))
409 	MTKSWITCH_LOCK(sc);
410 	if (sc->sc_switchtype == MTK_SWITCH_MT7620) {
411 		v->es_vid = (sc->hal.mtkswitch_read(sc,
418 	while (sc->hal.mtkswitch_read(sc, MTKSWITCH_VTCR) & VTCR_BUSY);
419 	sc->hal.mtkswitch_write(sc, MTKSWITCH_VTCR, VTCR_BUSY |
421 	while ((val = sc->hal.mtkswitch_read(sc, MTKSWITCH_VTCR)) & VTCR_BUSY);
423 		MTKSWITCH_UNLOCK(sc);
427 	val = sc->hal.mtkswitch_read(sc, MTKSWITCH_VAWD1);
431 		MTKSWITCH_UNLOCK(sc);
436 	val = sc->hal.mtkswitch_read(sc, MTKSWITCH_VAWD2);
437 	for (i = 0; i < sc->info.es_nports; i++) {
442 	MTKSWITCH_UNLOCK(sc);
447 mtkswitch_vlan_setvgroup(struct mtkswitch_softc *sc, etherswitch_vlangroup_t *v)
451 	MTKSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
453 	if ((sc->vlan_mode != ETHERSWITCH_VLAN_DOT1Q) ||
454 	    (v->es_vlangroup > sc->info.es_nvlangroups))
461 	MTKSWITCH_LOCK(sc);
462 	while (sc->hal.mtkswitch_read(sc, MTKSWITCH_VTCR) & VTCR_BUSY);
463 	if (sc->sc_switchtype == MTK_SWITCH_MT7620) {
464 		val = sc->hal.mtkswitch_read(sc,
468 		sc->hal.mtkswitch_write(sc, MTKSWITCH_VTIM(v->es_vlangroup),
477 	sc->hal.mtkswitch_write(sc, MTKSWITCH_VAWD1, val);
481 	for (i = 0; i < sc->info.es_nports; i++)
484 	sc->hal.mtkswitch_write(sc, MTKSWITCH_VAWD2, val);
487 	sc->hal.mtkswitch_write(sc, MTKSWITCH_VTCR, VTCR_BUSY |
489 	while ((val = sc->hal.mtkswitch_read(sc, MTKSWITCH_VTCR)) & VTCR_BUSY);
491 	MTKSWITCH_UNLOCK(sc);
500 mtkswitch_vlan_get_pvid(struct mtkswitch_softc *sc, int port, int *pvid)
503 	MTKSWITCH_LOCK_ASSERT(sc, MA_OWNED);
505 	*pvid = sc->hal.mtkswitch_read(sc, MTKSWITCH_PPBV1(port));
512 mtkswitch_vlan_set_pvid(struct mtkswitch_softc *sc, int port, int pvid)
516 	MTKSWITCH_LOCK_ASSERT(sc, MA_OWNED);
518 	sc->hal.mtkswitch_write(sc, MTKSWITCH_PPBV1(port), val);
519 	sc->hal.mtkswitch_write(sc, MTKSWITCH_PPBV2(port), val);
525 mtk_attach_switch_mt7620(struct mtkswitch_softc *sc)
528 	sc->portmap = 0x7f;
529 	sc->phymap = 0x1f;
531 	sc->info.es_nports = 7;
532 	sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q;
533 	sc->info.es_nvlangroups = 16;
534 	sprintf(sc->info.es_name, "Mediatek GSW");
536 	if (sc->sc_switchtype == MTK_SWITCH_MT7621) {
537 		sc->hal.mtkswitch_read = mtkswitch_reg_read32_mt7621;
538 		sc->hal.mtkswitch_write = mtkswitch_reg_write32_mt7621;
539 		sc->info.es_nvlangroups = 4096;
541 		sc->hal.mtkswitch_read = mtkswitch_reg_read32;
542 		sc->hal.mtkswitch_write = mtkswitch_reg_write32;
545 	sc->hal.mtkswitch_reset = mtkswitch_reset;
546 	sc->hal.mtkswitch_hw_setup = mtkswitch_hw_setup;
547 	sc->hal.mtkswitch_hw_global_setup = mtkswitch_hw_global_setup;
548 	sc->hal.mtkswitch_port_init = mtkswitch_port_init;
549 	sc->hal.mtkswitch_get_port_status = mtkswitch_get_port_status;
550 	sc->hal.mtkswitch_atu_flush = mtkswitch_atu_flush;
551 	sc->hal.mtkswitch_port_vlan_setup = mtkswitch_port_vlan_setup;
552 	sc->hal.mtkswitch_port_vlan_get = mtkswitch_port_vlan_get;
553 	sc->hal.mtkswitch_vlan_init_hw = mtkswitch_vlan_init_hw;
554 	sc->hal.mtkswitch_vlan_getvgroup = mtkswitch_vlan_getvgroup;
555 	sc->hal.mtkswitch_vlan_setvgroup = mtkswitch_vlan_setvgroup;
556 	sc->hal.mtkswitch_vlan_get_pvid = mtkswitch_vlan_get_pvid;
557 	sc->hal.mtkswitch_vlan_set_pvid = mtkswitch_vlan_set_pvid;
558 	sc->hal.mtkswitch_phy_read = mtkswitch_phy_read;
559 	sc->hal.mtkswitch_phy_write = mtkswitch_phy_write;
560 	sc->hal.mtkswitch_reg_read = mtkswitch_reg_read;
561 	sc->hal.mtkswitch_reg_write = mtkswitch_reg_write;