Lines Matching refs:cq
10 void vnic_cq_init(struct vnic_cq *cq, unsigned int flow_control_enable,
18 paddr = (u64)cq->ring.base_addr | VNIC_PADDR_TARGET;
19 ENIC_BUS_WRITE_8(cq->ctrl, CQ_RING_BASE, paddr);
20 ENIC_BUS_WRITE_4(cq->ctrl, CQ_RING_SIZE, cq->ring.desc_count);
21 ENIC_BUS_WRITE_4(cq->ctrl, CQ_FLOW_CONTROL_ENABLE, flow_control_enable);
22 ENIC_BUS_WRITE_4(cq->ctrl, CQ_COLOR_ENABLE, color_enable);
23 ENIC_BUS_WRITE_4(cq->ctrl, CQ_HEAD, cq_head);
24 ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL, cq_tail);
25 ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL_COLOR, cq_tail_color);
26 ENIC_BUS_WRITE_4(cq->ctrl, CQ_INTR_ENABLE, interrupt_enable);
27 ENIC_BUS_WRITE_4(cq->ctrl, CQ_ENTRY_ENABLE, cq_entry_enable);
28 ENIC_BUS_WRITE_4(cq->ctrl, CQ_MESSAGE_ENABLE, cq_message_enable);
29 ENIC_BUS_WRITE_4(cq->ctrl, CQ_INTR_OFFSET, interrupt_offset);
30 ENIC_BUS_WRITE_8(cq->ctrl, CQ_MESSAGE_ADDR, cq_message_addr);
32 cq->interrupt_offset = interrupt_offset;
35 void vnic_cq_clean(struct vnic_cq *cq)
37 cq->to_clean = 0;
38 cq->last_color = 0;
40 ENIC_BUS_WRITE_4(cq->ctrl, CQ_HEAD, 0);
41 ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL, 0);
42 ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL_COLOR, 1);
44 vnic_dev_clear_desc_ring(&cq->ring);