Lines Matching refs:ret_val
205 s32 ret_val = 0;
210 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
211 if (ret_val || (phy_reg == 0xFFFF))
215 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
216 if (ret_val || (phy_reg == 0xFFFF)) {
238 ret_val = e1000_set_mdio_slow_mode_hv(hw);
239 if (!ret_val)
240 ret_val = e1000_get_phy_id(hw);
244 if (ret_val)
320 s32 ret_val;
333 ret_val = e1000_disable_ulp_lpt_lp(hw, true);
334 if (ret_val)
337 ret_val = hw->phy.ops.acquire(hw);
338 if (ret_val) {
384 ret_val = -E1000_ERR_PHY;
404 ret_val = -E1000_ERR_PHY;
412 if (!ret_val) {
425 ret_val = e1000_phy_hw_reset_generic(hw);
426 if (ret_val)
435 ret_val = hw->phy.ops.check_reset_block(hw);
436 if (ret_val)
448 return ret_val;
460 s32 ret_val;
487 ret_val = e1000_init_phy_workarounds_pchlan(hw);
488 if (ret_val)
489 return ret_val;
494 ret_val = e1000_get_phy_id(hw);
495 if (ret_val)
496 return ret_val;
511 ret_val = e1000_set_mdio_slow_mode_hv(hw);
512 if (ret_val)
513 return ret_val;
514 ret_val = e1000_get_phy_id(hw);
515 if (ret_val)
516 return ret_val;
539 ret_val = -E1000_ERR_PHY;
543 return ret_val;
555 s32 ret_val;
579 ret_val = e1000_determine_phy_address(hw);
580 if (ret_val) {
583 ret_val = e1000_determine_phy_address(hw);
584 if (ret_val) {
586 return ret_val;
594 ret_val = e1000_get_phy_id(hw);
595 if (ret_val)
596 return ret_val;
858 s32 ret_val;
862 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
863 if (ret_val)
864 return ret_val;
867 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
870 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
873 return ret_val;
923 s32 ret_val;
943 ret_val = hw->phy.ops.acquire(hw);
944 if (ret_val)
945 return ret_val;
947 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
948 if (ret_val)
957 ret_val = e1000_read_emi_reg_locked(hw, lpa,
959 if (ret_val)
963 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
964 if (ret_val)
988 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
990 if (ret_val)
994 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
999 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
1000 if (ret_val)
1003 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
1007 return ret_val;
1025 s32 ret_val = E1000_SUCCESS;
1029 ret_val = hw->phy.ops.acquire(hw);
1030 if (ret_val)
1031 return ret_val;
1033 ret_val =
1036 if (ret_val)
1039 ret_val =
1044 if (ret_val)
1052 ret_val =
1067 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1068 if (ret_val)
1069 return ret_val;
1089 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1090 if (ret_val)
1091 return ret_val;
1097 return ret_val;
1275 s32 ret_val = E1000_SUCCESS;
1318 ret_val = hw->phy.ops.acquire(hw);
1319 if (ret_val)
1323 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1324 if (ret_val)
1338 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1340 if (ret_val)
1346 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1349 if (ret_val)
1356 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1357 if (ret_val)
1387 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1389 if (ret_val)
1396 if (ret_val)
1397 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1401 return ret_val;
1421 s32 ret_val = E1000_SUCCESS;
1450 ret_val = -E1000_ERR_PHY;
1472 ret_val = hw->phy.ops.acquire(hw);
1473 if (ret_val)
1481 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1482 if (ret_val) {
1492 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1494 if (ret_val)
1508 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1509 if (ret_val)
1515 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1516 if (ret_val)
1544 if (ret_val)
1545 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1549 return ret_val;
1563 s32 ret_val, tipg_reg = 0;
1582 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1583 if (ret_val)
1584 return ret_val;
1587 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1588 if (ret_val)
1589 return ret_val;
1619 ret_val = hw->phy.ops.acquire(hw);
1620 if (ret_val)
1621 return ret_val;
1627 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1654 if (ret_val)
1655 return ret_val;
1662 ret_val = hw->phy.ops.acquire(hw);
1663 if (ret_val)
1664 return ret_val;
1666 ret_val = hw->phy.ops.read_reg_locked(hw,
1669 if (ret_val) {
1671 return ret_val;
1678 ret_val =
1683 if (ret_val)
1684 return ret_val;
1686 ret_val = hw->phy.ops.acquire(hw);
1687 if (ret_val)
1688 return ret_val;
1690 ret_val = hw->phy.ops.write_reg_locked(hw,
1694 if (ret_val)
1695 return ret_val;
1720 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1721 if (ret_val)
1722 return ret_val;
1729 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1730 if (ret_val)
1731 return ret_val;
1765 ret_val = e1000_k1_workaround_lv(hw);
1766 if (ret_val)
1767 return ret_val;
1771 ret_val = e1000_link_stall_workaround_hv(hw);
1772 if (ret_val)
1773 return ret_val;
1801 ret_val = e1000_set_eee_pchlan(hw);
1802 if (ret_val)
1803 return ret_val;
1823 ret_val = e1000_config_fc_after_link_up_generic(hw);
1824 if (ret_val)
1827 return ret_val;
1902 s32 ret_val = E1000_SUCCESS;
1919 ret_val = -E1000_ERR_CONFIG;
1942 ret_val = -E1000_ERR_CONFIG;
1947 return ret_val;
2056 s32 ret_val;
2058 ret_val = e1000_acquire_swflag_ich8lan(hw);
2059 if (ret_val)
2134 s32 ret_val;
2136 ret_val = e1000_acquire_swflag_ich8lan(hw);
2138 if (ret_val)
2177 s32 ret_val;
2183 ret_val = hw->phy.ops.acquire(hw);
2184 if (ret_val)
2187 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2188 if (ret_val)
2247 s32 ret_val;
2251 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2252 if (ret_val)
2253 return ret_val;
2286 s32 ret_val = E1000_SUCCESS;
2300 return ret_val;
2320 return ret_val;
2323 ret_val = hw->phy.ops.acquire(hw);
2324 if (ret_val)
2325 return ret_val;
2356 ret_val = e1000_write_smbus_addr(hw);
2357 if (ret_val)
2361 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2363 if (ret_val)
2373 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2375 if (ret_val)
2378 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2380 if (ret_val)
2392 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2394 if (ret_val)
2400 return ret_val;
2415 s32 ret_val = E1000_SUCCESS;
2425 ret_val = hw->phy.ops.acquire(hw);
2426 if (ret_val)
2427 return ret_val;
2432 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2434 if (ret_val)
2448 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2450 if (ret_val)
2464 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2466 if (ret_val)
2471 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2473 if (ret_val)
2477 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2482 return ret_val;
2497 s32 ret_val;
2505 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2507 if (ret_val)
2508 return ret_val;
2515 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2517 if (ret_val)
2518 return ret_val;
2550 s32 ret_val = 0;
2557 return ret_val;
2559 ret_val = hw->phy.ops.acquire(hw);
2560 if (ret_val)
2561 return ret_val;
2575 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2576 if (ret_val)
2602 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2607 return ret_val;
2617 s32 ret_val;
2622 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2623 if (ret_val)
2624 return ret_val;
2628 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2630 return ret_val;
2640 s32 ret_val = E1000_SUCCESS;
2650 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2651 if (ret_val)
2652 return ret_val;
2659 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2660 if (ret_val)
2661 return ret_val;
2664 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2666 if (ret_val)
2667 return ret_val;
2676 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2678 if (ret_val)
2679 return ret_val;
2684 ret_val = hw->phy.ops.acquire(hw);
2685 if (ret_val)
2686 return ret_val;
2689 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2691 if (ret_val)
2692 return ret_val;
2697 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2698 if (ret_val)
2699 return ret_val;
2702 ret_val = hw->phy.ops.acquire(hw);
2703 if (ret_val)
2704 return ret_val;
2705 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2706 if (ret_val)
2708 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2710 if (ret_val)
2714 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2718 return ret_val;
2729 s32 ret_val;
2733 ret_val = hw->phy.ops.acquire(hw);
2734 if (ret_val)
2736 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2737 if (ret_val)
2788 s32 ret_val = E1000_SUCCESS;
2800 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2802 if (ret_val)
2803 return ret_val;
2841 ret_val = e1000_read_kmrn_reg_generic(hw,
2844 if (ret_val)
2845 return ret_val;
2846 ret_val = e1000_write_kmrn_reg_generic(hw,
2849 if (ret_val)
2850 return ret_val;
2851 ret_val = e1000_read_kmrn_reg_generic(hw,
2854 if (ret_val)
2855 return ret_val;
2858 ret_val = e1000_write_kmrn_reg_generic(hw,
2861 if (ret_val)
2862 return ret_val;
2868 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2869 if (ret_val)
2870 return ret_val;
2873 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2874 if (ret_val)
2875 return ret_val;
2879 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2880 if (ret_val)
2881 return ret_val;
2882 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2883 if (ret_val)
2884 return ret_val;
2886 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2888 if (ret_val)
2889 return ret_val;
2900 ret_val = e1000_read_kmrn_reg_generic(hw,
2903 if (ret_val)
2904 return ret_val;
2905 ret_val = e1000_write_kmrn_reg_generic(hw,
2908 if (ret_val)
2909 return ret_val;
2910 ret_val = e1000_read_kmrn_reg_generic(hw,
2913 if (ret_val)
2914 return ret_val;
2917 ret_val = e1000_write_kmrn_reg_generic(hw,
2920 if (ret_val)
2921 return ret_val;
2926 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2927 if (ret_val)
2928 return ret_val;
2931 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2932 if (ret_val)
2933 return ret_val;
2937 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2938 if (ret_val)
2939 return ret_val;
2940 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2941 if (ret_val)
2942 return ret_val;
2944 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2946 if (ret_val)
2947 return ret_val;
2962 s32 ret_val = E1000_SUCCESS;
2970 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2971 if (ret_val)
2972 return ret_val;
2974 ret_val = hw->phy.ops.acquire(hw);
2975 if (ret_val)
2976 return ret_val;
2978 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2979 if (ret_val)
2982 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2986 return ret_val;
2998 s32 ret_val = E1000_SUCCESS;
3007 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
3008 if (ret_val)
3009 return ret_val;
3018 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
3020 if (ret_val)
3021 return ret_val;
3023 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
3025 if (ret_val)
3026 return ret_val;
3036 return ret_val;
3105 s32 ret_val = E1000_SUCCESS;
3119 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3120 if (ret_val)
3121 return ret_val;
3124 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3125 if (ret_val)
3126 return ret_val;
3140 ret_val = e1000_sw_lcd_config_ich8lan(hw);
3141 if (ret_val)
3142 return ret_val;
3145 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
3156 ret_val = hw->phy.ops.acquire(hw);
3157 if (ret_val)
3158 return ret_val;
3159 ret_val = e1000_write_emi_reg_locked(hw,
3165 return ret_val;
3178 s32 ret_val = E1000_SUCCESS;
3187 ret_val = e1000_phy_hw_reset_generic(hw);
3188 if (ret_val)
3189 return ret_val;
3207 s32 ret_val;
3211 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3212 if (ret_val)
3213 return ret_val;
3243 s32 ret_val = E1000_SUCCESS;
3267 ret_val = phy->ops.read_reg(hw,
3270 if (ret_val)
3271 return ret_val;
3273 ret_val = phy->ops.write_reg(hw,
3276 if (ret_val)
3277 return ret_val;
3291 ret_val = phy->ops.read_reg(hw,
3294 if (ret_val)
3295 return ret_val;
3298 ret_val = phy->ops.write_reg(hw,
3301 if (ret_val)
3302 return ret_val;
3304 ret_val = phy->ops.read_reg(hw,
3307 if (ret_val)
3308 return ret_val;
3311 ret_val = phy->ops.write_reg(hw,
3314 if (ret_val)
3315 return ret_val;
3339 s32 ret_val = E1000_SUCCESS;
3359 ret_val = phy->ops.read_reg(hw,
3362 if (ret_val)
3363 return ret_val;
3366 ret_val = phy->ops.write_reg(hw,
3369 if (ret_val)
3370 return ret_val;
3372 ret_val = phy->ops.read_reg(hw,
3375 if (ret_val)
3376 return ret_val;
3379 ret_val = phy->ops.write_reg(hw,
3382 if (ret_val)
3383 return ret_val;
3401 ret_val = phy->ops.read_reg(hw,
3404 if (ret_val)
3405 return ret_val;
3408 ret_val = phy->ops.write_reg(hw,
3413 return ret_val;
3432 s32 ret_val;
3450 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3452 if (ret_val)
3453 return ret_val;
3462 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3465 if (ret_val)
3466 return ret_val;
3495 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3497 if (ret_val)
3498 return ret_val;
3506 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3509 if (ret_val)
3510 return ret_val;
3537 s32 ret_val = E1000_SUCCESS;
3548 ret_val = -E1000_ERR_NVM;
3554 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3555 if (ret_val != E1000_SUCCESS) {
3563 ret_val = E1000_SUCCESS;
3573 ret_val =
3577 if (ret_val)
3588 ret_val =
3592 if (ret_val)
3611 if (ret_val)
3612 DEBUGOUT1("NVM read error: %d\n", ret_val);
3614 return ret_val;
3632 s32 ret_val = E1000_SUCCESS;
3641 ret_val = -E1000_ERR_NVM;
3647 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3648 if (ret_val != E1000_SUCCESS) {
3656 ret_val = E1000_SUCCESS;
3661 ret_val = e1000_read_flash_word_ich8lan(hw,
3664 if (ret_val)
3673 if (ret_val)
3674 DEBUGOUT1("NVM read error: %d\n", ret_val);
3676 return ret_val;
3689 s32 ret_val = -E1000_ERR_NVM;
3730 ret_val = E1000_SUCCESS;
3741 ret_val = E1000_SUCCESS;
3746 if (ret_val == E1000_SUCCESS) {
3762 return ret_val;
3864 s32 ret_val;
3873 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3875 if (ret_val)
3876 return ret_val;
3899 s32 ret_val = -E1000_ERR_NVM;
3912 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3913 if (ret_val != E1000_SUCCESS)
3923 ret_val = e1000_flash_cycle_ich8lan(hw,
3931 if (ret_val == E1000_SUCCESS) {
3956 return ret_val;
3973 s32 ret_val = -E1000_ERR_NVM;
3987 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3988 if (ret_val != E1000_SUCCESS)
4005 ret_val = e1000_flash_cycle_ich8lan(hw,
4013 if (ret_val == E1000_SUCCESS) {
4034 return ret_val;
4089 s32 ret_val;
4094 ret_val = e1000_update_nvm_checksum_generic(hw);
4095 if (ret_val)
4107 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4108 if (ret_val != E1000_SUCCESS) {
4116 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4117 if (ret_val)
4122 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4123 if (ret_val)
4131 ret_val = e1000_read_flash_dword_ich8lan(hw,
4144 if (ret_val)
4164 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4166 if (ret_val)
4173 if (ret_val) {
4187 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4189 if (ret_val)
4193 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4195 if (ret_val)
4200 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4202 if (ret_val)
4206 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4208 if (ret_val)
4223 if (!ret_val) {
4229 if (ret_val)
4230 DEBUGOUT1("NVM update error: %d\n", ret_val);
4232 return ret_val;
4251 s32 ret_val;
4256 ret_val = e1000_update_nvm_checksum_generic(hw);
4257 if (ret_val)
4269 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4270 if (ret_val != E1000_SUCCESS) {
4278 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4279 if (ret_val)
4284 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4285 if (ret_val)
4292 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4295 if (ret_val)
4314 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4317 if (ret_val)
4321 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4324 if (ret_val)
4331 if (ret_val) {
4342 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4343 if (ret_val)
4347 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4349 if (ret_val)
4359 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4361 if (ret_val)
4376 if (!ret_val) {
4382 if (ret_val)
4383 DEBUGOUT1("NVM update error: %d\n", ret_val);
4385 return ret_val;
4398 s32 ret_val;
4427 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4428 if (ret_val)
4429 return ret_val;
4433 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4434 if (ret_val)
4435 return ret_val;
4436 ret_val = hw->nvm.ops.update(hw);
4437 if (ret_val)
4438 return ret_val;
4460 s32 ret_val;
4479 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4480 if (ret_val != E1000_SUCCESS)
4518 ret_val =
4521 if (ret_val == E1000_SUCCESS)
4539 return ret_val;
4556 s32 ret_val;
4570 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4571 if (ret_val != E1000_SUCCESS)
4606 ret_val = e1000_flash_cycle_ich8lan(hw,
4609 if (ret_val == E1000_SUCCESS)
4628 return ret_val;
4661 s32 ret_val;
4669 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4671 if (!ret_val)
4672 return ret_val;
4676 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4677 if (ret_val == E1000_SUCCESS)
4698 s32 ret_val;
4703 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4704 if (!ret_val)
4705 return ret_val;
4710 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4711 if (ret_val == E1000_SUCCESS)
4736 s32 ret_val;
4787 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4788 if (ret_val)
4789 return ret_val;
4819 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4820 if (ret_val == E1000_SUCCESS)
4833 return ret_val;
4851 s32 ret_val;
4855 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4856 if (ret_val) {
4858 return ret_val;
4883 s32 ret_val;
4891 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4892 if (ret_val)
4893 return ret_val;
4951 s32 ret_val;
4955 ret_val = e1000_get_bus_info_pcie_generic(hw);
4965 return ret_val;
4980 s32 ret_val;
4988 ret_val = e1000_disable_pcie_master_generic(hw);
4989 if (ret_val)
5015 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
5016 if (ret_val)
5017 return ret_val;
5041 ret_val = e1000_acquire_swflag_ich8lan(hw);
5074 ret_val = hw->phy.ops.get_cfg_done(hw);
5075 if (ret_val)
5076 return ret_val;
5078 ret_val = e1000_post_phy_reset_ich8lan(hw);
5079 if (ret_val)
5080 return ret_val;
5116 s32 ret_val;
5124 ret_val = mac->ops.id_led_init(hw);
5126 if (ret_val)
5145 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5146 if (ret_val)
5147 return ret_val;
5151 ret_val = mac->ops.setup_link(hw);
5194 return ret_val;
5290 s32 ret_val;
5311 ret_val = hw->mac.ops.setup_physical_interface(hw);
5312 if (ret_val)
5313 return ret_val;
5323 ret_val = hw->phy.ops.write_reg(hw,
5326 if (ret_val)
5327 return ret_val;
5344 s32 ret_val;
5358 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5360 if (ret_val)
5361 return ret_val;
5362 ret_val = e1000_read_kmrn_reg_generic(hw,
5365 if (ret_val)
5366 return ret_val;
5368 ret_val = e1000_write_kmrn_reg_generic(hw,
5371 if (ret_val)
5372 return ret_val;
5376 ret_val = e1000_copper_link_setup_igp(hw);
5377 if (ret_val)
5378 return ret_val;
5382 ret_val = e1000_copper_link_setup_m88(hw);
5383 if (ret_val)
5384 return ret_val;
5388 ret_val = e1000_copper_link_setup_82577(hw);
5389 if (ret_val)
5390 return ret_val;
5393 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5395 if (ret_val)
5396 return ret_val;
5412 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5414 if (ret_val)
5415 return ret_val;
5435 s32 ret_val;
5444 ret_val = e1000_copper_link_setup_82577(hw);
5445 if (ret_val)
5446 return ret_val;
5464 s32 ret_val;
5468 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5469 if (ret_val)
5470 return ret_val;
5475 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5478 return ret_val;
5500 s32 ret_val;
5513 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5519 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5520 if (ret_val)
5521 return ret_val;
5523 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5524 if (ret_val)
5525 return ret_val;
5641 s32 ret_val;
5650 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5652 if (ret_val)
5655 ret_val = e1000_write_kmrn_reg_generic(hw,
5658 if (ret_val)
5683 s32 ret_val;
5704 ret_val = hw->phy.ops.acquire(hw);
5705 if (ret_val)
5711 ret_val =
5715 if (ret_val)
5793 ret_val = hw->phy.ops.acquire(hw);
5794 if (ret_val)
5815 s32 ret_val;
5821 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5822 if (ret_val) {
5823 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5824 return ret_val;
5835 ret_val = hw->phy.ops.acquire(hw);
5836 if (ret_val) {
5838 return ret_val;
5851 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5853 if (ret_val)
5862 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5864 if (ret_val)
5869 if (ret_val)
5870 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5872 return ret_val;
6037 s32 ret_val = E1000_SUCCESS;
6049 ret_val = e1000_get_auto_rd_done_generic(hw);
6050 if (ret_val) {
6056 ret_val = E1000_SUCCESS;
6077 ret_val = -E1000_ERR_CONFIG;
6081 return ret_val;
6111 s32 ret_val;
6136 ret_val = hw->phy.ops.acquire(hw);
6137 if (ret_val)
6139 ret_val = hw->phy.ops.set_page(hw,
6141 if (ret_val)
6179 s32 ret_val;
6187 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6189 if (ret_val)
6190 return ret_val;
6196 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6198 if (ret_val)
6199 return ret_val;