Lines Matching refs:ret_val
161 s32 ret_val = E1000_SUCCESS;
222 ret_val = e1000_get_phy_id_82575(hw);
275 ret_val = -E1000_ERR_PHY;
285 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 2);
286 if (ret_val)
288 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_MAC_CTRL_1,
290 if (ret_val)
303 ret_val = e1000_initialize_M88E1512_phy(hw);
308 ret_val = e1000_initialize_M88E1543_phy(hw);
316 return ret_val;
547 s32 ret_val = -E1000_ERR_PARAM;
556 ret_val = hw->phy.ops.acquire(hw);
557 if (ret_val)
560 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
565 return ret_val;
580 s32 ret_val = -E1000_ERR_PARAM;
589 ret_val = hw->phy.ops.acquire(hw);
590 if (ret_val)
593 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
598 return ret_val;
611 s32 ret_val = E1000_SUCCESS;
631 ret_val = e1000_get_phy_id(hw);
653 ret_val = -E1000_ERR_PHY;
657 ret_val = e1000_get_phy_id(hw);
673 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
674 if (ret_val == E1000_SUCCESS) {
692 ret_val = -E1000_ERR_PHY;
694 ret_val = e1000_get_phy_id(hw);
701 return ret_val;
712 s32 ret_val = E1000_SUCCESS;
731 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
732 if (ret_val)
735 ret_val = hw->phy.ops.commit(hw);
736 if (ret_val)
740 ret_val = e1000_initialize_M88E1512_phy(hw);
742 return ret_val;
761 s32 ret_val = E1000_SUCCESS;
769 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
770 if (ret_val)
775 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
777 if (ret_val)
781 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
784 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
786 if (ret_val)
790 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
799 ret_val = phy->ops.read_reg(hw,
802 if (ret_val)
806 ret_val = phy->ops.write_reg(hw,
809 if (ret_val)
812 ret_val = phy->ops.read_reg(hw,
815 if (ret_val)
819 ret_val = phy->ops.write_reg(hw,
822 if (ret_val)
828 return ret_val;
935 s32 ret_val = E1000_SUCCESS;
939 ret_val = e1000_acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
940 if (ret_val)
968 ret_val = e1000_acquire_nvm_generic(hw);
969 if (ret_val)
973 return ret_val;
1045 s32 ret_val;
1050 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1053 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1056 return ret_val;
1068 s32 ret_val;
1074 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1089 ret_val = e1000_config_fc_after_link_up_generic(hw);
1090 if (ret_val)
1093 ret_val = e1000_check_for_copper_link_generic(hw);
1096 return ret_val;
1108 s32 ret_val;
1115 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1116 if (ret_val)
1117 return ret_val;
1119 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1120 if (ret_val)
1121 return ret_val;
1127 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1128 if (ret_val)
1129 return ret_val;
1131 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1132 if (ret_val)
1133 return ret_val;
1146 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1147 if (ret_val)
1148 return ret_val;
1153 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1154 if (ret_val)
1155 return ret_val;
1301 s32 ret_val;
1309 ret_val = e1000_disable_pcie_master_generic(hw);
1310 if (ret_val)
1314 ret_val = e1000_set_pcie_completion_timeout(hw);
1315 if (ret_val)
1332 ret_val = e1000_get_auto_rd_done_generic(hw);
1333 if (ret_val) {
1351 ret_val = e1000_check_alt_mac_addr_generic(hw);
1353 return ret_val;
1365 s32 ret_val;
1370 ret_val = mac->ops.id_led_init(hw);
1371 if (ret_val) {
1380 ret_val = e1000_init_hw_base(hw);
1392 return ret_val;
1406 s32 ret_val;
1429 ret_val = e1000_setup_serdes_link_82575(hw);
1430 if (ret_val)
1437 ret_val = hw->phy.ops.reset(hw);
1438 if (ret_val) {
1459 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1462 ret_val = e1000_copper_link_setup_m88(hw);
1467 ret_val = e1000_copper_link_setup_igp(hw);
1470 ret_val = e1000_copper_link_setup_82577(hw);
1473 ret_val = -E1000_ERR_PHY;
1477 if (ret_val)
1480 ret_val = e1000_setup_copper_link_generic(hw);
1482 return ret_val;
1498 s32 ret_val = E1000_SUCCESS;
1505 return ret_val;
1546 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1547 if (ret_val) {
1549 return ret_val;
1623 return ret_val;
1640 s32 ret_val = E1000_SUCCESS;
1672 ret_val = e1000_set_sfp_media_type_82575(hw);
1673 if ((ret_val != E1000_SUCCESS) ||
1706 return ret_val;
1718 s32 ret_val = E1000_ERR_CONFIG;
1734 ret_val = e1000_read_sfp_data_byte(hw,
1737 if (ret_val == E1000_SUCCESS)
1742 if (ret_val != E1000_SUCCESS)
1745 ret_val = e1000_read_sfp_data_byte(hw,
1748 if (ret_val != E1000_SUCCESS)
1771 ret_val = E1000_SUCCESS;
1775 return ret_val;
1788 s32 ret_val;
1792 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1793 if (ret_val) {
1810 return ret_val;
1871 s32 ret_val;
1880 ret_val = e1000_check_alt_mac_addr_generic(hw);
1881 if (ret_val)
1884 ret_val = e1000_read_mac_addr_generic(hw);
1887 return ret_val;
1990 s32 ret_val = E1000_SUCCESS;
2011 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2013 if (ret_val)
2018 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2025 return ret_val;
2134 s32 ret_val;
2138 ret_val = hw->phy.ops.acquire(hw);
2139 if (ret_val)
2142 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2147 return ret_val;
2160 s32 ret_val;
2164 ret_val = hw->phy.ops.acquire(hw);
2165 if (ret_val)
2168 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2173 return ret_val;
2186 s32 ret_val = E1000_SUCCESS;
2197 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2200 if (ret_val) {
2212 return ret_val;
2224 s32 ret_val = E1000_SUCCESS;
2245 ret_val = e1000_disable_pcie_master_generic(hw);
2246 if (ret_val)
2281 ret_val = e1000_get_auto_rd_done_generic(hw);
2282 if (ret_val) {
2298 ret_val = e1000_reset_mdicnfg_82580(hw);
2299 if (ret_val)
2303 ret_val = e1000_check_alt_mac_addr_generic(hw);
2309 return ret_val;
2324 u16 ret_val = 0;
2327 ret_val = e1000_82580_rxpbs_table[data];
2329 return ret_val;
2343 s32 ret_val = E1000_SUCCESS;
2350 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2351 if (ret_val) {
2360 ret_val = -E1000_ERR_NVM;
2365 return ret_val;
2380 s32 ret_val;
2387 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2388 if (ret_val) {
2395 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2397 if (ret_val)
2401 return ret_val;
2414 s32 ret_val;
2421 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2422 if (ret_val) {
2435 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2437 if (ret_val != E1000_SUCCESS)
2442 return ret_val;
2455 s32 ret_val;
2461 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2462 if (ret_val) {
2470 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2472 if (ret_val) {
2480 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2481 if (ret_val)
2486 return ret_val;
2499 s32 ret_val = E1000_SUCCESS;
2507 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2509 if (ret_val != E1000_SUCCESS)
2514 return ret_val;
2527 s32 ret_val = E1000_SUCCESS;
2535 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2536 if (ret_val != E1000_SUCCESS)
2541 return ret_val;
2554 s32 ret_val;
2558 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2559 if (ret_val)
2560 return ret_val;
2563 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2565 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2567 return ret_val;
2592 s32 ret_val = E1000_SUCCESS;
2601 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2602 if (ret_val)
2605 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2606 if (ret_val)
2609 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2610 if (ret_val)
2613 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2614 if (ret_val)
2617 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2618 if (ret_val)
2621 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2622 if (ret_val)
2625 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2626 if (ret_val)
2629 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2630 if (ret_val)
2633 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2634 if (ret_val)
2638 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2639 if (ret_val)
2642 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2643 if (ret_val)
2647 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2648 if (ret_val)
2652 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2653 if (ret_val)
2657 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2658 if (ret_val)
2661 ret_val = phy->ops.commit(hw);
2662 if (ret_val) {
2664 return ret_val;
2669 return ret_val;
2681 s32 ret_val = E1000_SUCCESS;
2690 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2691 if (ret_val)
2694 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2695 if (ret_val)
2698 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2699 if (ret_val)
2702 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2703 if (ret_val)
2706 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2707 if (ret_val)
2710 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2711 if (ret_val)
2714 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2715 if (ret_val)
2718 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2719 if (ret_val)
2722 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2723 if (ret_val)
2727 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2728 if (ret_val)
2731 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2732 if (ret_val)
2736 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2737 if (ret_val)
2741 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2742 if (ret_val)
2746 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2747 if (ret_val)
2751 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2752 if (ret_val)
2756 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2757 if (ret_val)
2760 ret_val = phy->ops.commit(hw);
2761 if (ret_val) {
2763 return ret_val;
2768 return ret_val;
2838 s32 ret_val = E1000_SUCCESS;
2850 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2851 if (ret_val)
2854 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2856 if (ret_val)
2860 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2862 if (ret_val)
2866 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2867 if (ret_val)
2871 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2874 if (ret_val)
2887 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2892 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2895 if (ret_val)
2900 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2906 return ret_val;
2920 s32 ret_val = E1000_SUCCESS;
2931 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2934 if (ret_val)
2941 return ret_val;
3002 s32 ret_val = E1000_SUCCESS;
3019 return ret_val;