dev/e1000/e1000_82571.c

94 	s32 ret_val;
164 	ret_val = e1000_get_phy_id_82571(hw);
165 	if (ret_val) {
167 		return ret_val;
175 			ret_val = -E1000_ERR_PHY;
179 			ret_val = -E1000_ERR_PHY;
184 			ret_val = -E1000_ERR_PHY;
187 		ret_val = -E1000_ERR_PHY;
191 	if (ret_val)
194 	return ret_val;
463 	s32 ret_val;
483 		ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
484 		if (ret_val)
485 			return ret_val;
489 		ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
490 		if (ret_val)
491 			return ret_val;
629 	s32 ret_val;
633 	ret_val = e1000_get_hw_semaphore(hw);
634 	if (ret_val)
635 		return ret_val;
641 		ret_val = e1000_acquire_nvm_generic(hw);
645 	if (ret_val)
648 	return ret_val;
680 	s32 ret_val;
688 		ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
692 		ret_val = e1000_write_nvm_spi(hw, offset, words, data);
695 		ret_val = -E1000_ERR_NVM;
699 	return ret_val;
713 	s32 ret_val;
718 	ret_val = e1000_update_nvm_checksum_generic(hw);
719 	if (ret_val)
720 		return ret_val;
800 	s32 ret_val = E1000_SUCCESS;
818 		ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
819 		if (ret_val)
824 		ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
825 		if (ret_val)
829 	return ret_val;
873 	s32 ret_val;
881 	ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
882 	if (ret_val)
883 		return ret_val;
887 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
889 		if (ret_val)
890 			return ret_val;
893 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
895 		if (ret_val)
896 			return ret_val;
898 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
900 		if (ret_val)
901 			return ret_val;
904 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
912 			ret_val = phy->ops.read_reg(hw,
915 			if (ret_val)
916 				return ret_val;
919 			ret_val = phy->ops.write_reg(hw,
922 			if (ret_val)
923 				return ret_val;
925 			ret_val = phy->ops.read_reg(hw,
928 			if (ret_val)
929 				return ret_val;
932 			ret_val = phy->ops.write_reg(hw,
935 			if (ret_val)
936 				return ret_val;
952 	s32 ret_val;
959 	ret_val = e1000_disable_pcie_master_generic(hw);
960 	if (ret_val)
981 		ret_val = e1000_get_hw_semaphore_82574(hw);
998 		if (!ret_val)
1014 	ret_val = e1000_get_auto_rd_done_generic(hw);
1015 	if (ret_val)
1017 		return ret_val;
1049 		ret_val = e1000_check_alt_mac_addr_generic(hw);
1050 		if (ret_val)
1051 			return ret_val;
1073 	s32 ret_val;
1081 	ret_val = mac->ops.id_led_init(hw);
1083 	if (ret_val)
1105 	ret_val = mac->ops.setup_link(hw);
1140 	return ret_val;
1335 	s32 ret_val;
1339 	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1340 	if (ret_val)
1384 	s32 ret_val;
1391 	ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1393 	if (ret_val)
1396 		ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1398 		if (ret_val)
1452 	s32 ret_val;
1464 		ret_val = e1000_copper_link_setup_m88(hw);
1467 		ret_val = e1000_copper_link_setup_igp(hw);
1474 	if (ret_val)
1475 		return ret_val;
1537 	s32 ret_val = E1000_SUCCESS;
1613 				ret_val =
1615 				if (ret_val) {
1679 	return ret_val;
1692 	s32 ret_val;
1696 	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1697 	if (ret_val) {
1699 		return ret_val;
1777 	s32 ret_val;
1788 	ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1789 	if (ret_val)
1790 		return ret_val;
1800 		ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1801 		if (ret_val)
1802 			return ret_val;
1806 			ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1807 			if (ret_val)
1808 				return ret_val;
1809 			ret_val = nvm->ops.update(hw);
1810 			if (ret_val)
1811 				return ret_val;
1828 		s32 ret_val;
1834 		ret_val = e1000_check_alt_mac_addr_generic(hw);
1835 		if (ret_val)
1836 			return ret_val;