dev/cxgbe/t4_main.c

1185 	int rc = 0, i, j, rqidx, tqidx, nports;
1448 	nports = sc->params.nports;
1458 	s->nrxq = nports * iaq.nrxq;
1459 	s->ntxq = nports * iaq.ntxq;
1461 		s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi;
1462 		s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi;
1465 	s->neq += nports;		/* ctrl queues: 1 per port */
1469 		s->nofldtxq = nports * iaq.nofldtxq;
1471 			s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi;
1480 		s->nofldrxq = nports * iaq.nofldrxq;
1482 			s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi;
1494 		s->nnmrxq += nports * iaq.nnmrxq;
1495 		s->nnmtxq += nports * iaq.nnmtxq;
1498 		s->nnmrxq += nports * (num_vis - 1) * iaq.nnmrxq_vi;
1499 		s->nnmtxq += nports * (num_vis - 1) * iaq.nnmtxq_vi;
1512 	s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE,
1645 	    sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
4246 update_nirq(struct intrs_and_queues *iaq, int nports)
4250 	iaq->nirq += nports * max(iaq->nrxq, iaq->nnmrxq);
4251 	iaq->nirq += nports * iaq->nofldrxq;
4252 	iaq->nirq += nports * (iaq->num_vis - 1) *
4254 	iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi;
4265 	const int nports = sc->params.nports;
4267 	MPASS(nports > 0);
4300 	update_nirq(iaq, nports);
4316 		update_nirq(iaq, nports);
4362 		update_nirq(iaq, nports);
5178 	sc->params.nports = bitcount32(val[0]);
6544 		KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
6547 		KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
6689 	MPASS(sc->params.nports <= nitems(sc->tq));
6690 	for (i = 0; i < sc->params.nports; i++) {
7341 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
7342 	    sc->params.nports, "# of ports");
11937 	if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
11972 	if (port_id >= sc->params.nports)