cxgbe/common/t4_hw.c

4198 		{ F_CCNTPERR, "PCIe CMD channel count parity error" },
4199 		{ F_CREQPERR, "PCIe CMD channel request parity error" },
4200 		{ F_CRSPPERR, "PCIe CMD channel response parity error" },
4201 		{ F_DCNTPERR, "PCIe DMA channel count parity error" },
4202 		{ F_DREQPERR, "PCIe DMA channel request parity error" },
4203 		{ F_DRSPPERR, "PCIe DMA channel response parity error" },
4204 		{ F_HCNTPERR, "PCIe HMA channel count parity error" },
4205 		{ F_HREQPERR, "PCIe HMA channel request parity error" },
4206 		{ F_HRSPPERR, "PCIe HMA channel response parity error" },
4234 		{ F_HRSPPERR, "HMA channel response data SRAM parity error" },
4235 		{ F_HREQRDPERR, "HMA channel read request SRAM parity error" },
4236 		{ F_HREQWRPERR, "HMA channel write request SRAM parity error" },
4237 		{ F_DRSPPERR, "DMA channel response data SRAM parity error" },
4238 		{ F_DREQRDPERR, "DMA channel write request SRAM parity error" },
4239 		{ F_CRSPPERR, "CMD channel response data SRAM parity error" },
4240 		{ F_CREQRDPERR, "CMD channel read request SRAM parity error" },
4346 		{ F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" },
4381 		{ F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" },
4609 		{ F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" },
4610 		{ F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" },
4613 		{ F_CAUSE_CTX_1, "ULPRX channel 1 context error" },
4614 		{ F_CAUSE_CTX_0, "ULPRX channel 0 context error" },
4650 		{ F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" },
4651 		{ F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" },
4652 		{ F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" },
4653 		{ F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" },
4708 		{ F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" },
4709 		{ F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" },
4710 		{ F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" },
6524  *	t4_get_chan_txrate - get the current per channel Tx rates
6530  *	for each channel.
6592 		 * capture size is 2.5KB (FIFO size of a single channel)
6773  * TP RX c-channel associated with the port.
6783  * TP TX c-channel associated with the port.
7840  *	@cmask: the channel access rights mask for the PF/VF
11128 		    int rateunit, int ratemode, int channel, int cl,
11144 	cmd.u.params.ch = channel;
11158 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode,
11172 	cmd.u.params.ch = channel;
11180 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl,
11197 	cmd.u.params.ch = channel;
11205 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl,
11220 	cmd.u.params.ch = channel;