dev/axgbe/xgbe-phy-v1.c

137 xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
139 	XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 1);
143 xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
145 	XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 0);
149 xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
151 	struct xgbe_phy_data *phy_data = pdata->phy_data;
155 	XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
156 	XGBE_SET_LP_ADV(&pdata->phy, Backplane);
159 	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
160 	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
162 		XGBE_SET_LP_ADV(&pdata->phy, Pause);
164 		XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
167 	    __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);
169 	if (pdata->phy.pause_autoneg) {
171 		pdata->phy.tx_pause = 0;
172 		pdata->phy.rx_pause = 0;
175 			pdata->phy.tx_pause = 1;
176 			pdata->phy.rx_pause = 1;
179 				pdata->phy.rx_pause = 1;
181 				pdata->phy.tx_pause = 1;
186 	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
187 	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
189 		XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);
192 			XGBE_SET_LP_ADV(&pdata->phy, 2500baseX_Full);
194 			XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);
199 		pdata->phy.speed = SPEED_10000;
202 		switch (pdata->speed_set) {
204 			pdata->phy.speed = SPEED_1000;
209 			pdata->phy.speed = SPEED_2500;
215 		pdata->phy.speed = SPEED_UNKNOWN;
219 	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
220 	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
222 		XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);
228 xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, struct xgbe_phy *dphy)
230 	XGBE_LM_COPY(dphy, advertising, &pdata->phy, advertising);
234 xgbe_phy_an_config(struct xgbe_prv_data *pdata)
241 xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
247 xgbe_phy_pcs_power_cycle(struct xgbe_prv_data *pdata)
251 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
254 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
259 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
263 xgbe_phy_start_ratechange(struct xgbe_prv_data *pdata)
266 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 1);
270 xgbe_phy_complete_ratechange(struct xgbe_prv_data *pdata)
276 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 0);
283 		status = XSIR0_IOREAD(pdata, SIR0_STATUS);
293 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 0);
294 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 1);
298 xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
300 	struct xgbe_phy_data *phy_data = pdata->phy_data;
304 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
307 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
309 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
312 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
314 	xgbe_phy_pcs_power_cycle(pdata);
317 	xgbe_phy_start_ratechange(pdata);
319 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_10000_RATE);
320 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_10000_WORD);
321 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_10000_PLL);
323 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
325 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
327 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
329 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
331 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
333 	XRXTX_IOWRITE(pdata, RXTX_REG22,
336 	xgbe_phy_complete_ratechange(pdata);
342 xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
344 	struct xgbe_phy_data *phy_data = pdata->phy_data;
348 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
351 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
353 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
356 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
358 	xgbe_phy_pcs_power_cycle(pdata);
361 	xgbe_phy_start_ratechange(pdata);
363 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_2500_RATE);
364 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_2500_WORD);
365 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_2500_PLL);
367 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
369 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
371 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
373 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
375 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
377 	XRXTX_IOWRITE(pdata, RXTX_REG22,
380 	xgbe_phy_complete_ratechange(pdata);
386 xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
388 	struct xgbe_phy_data *phy_data = pdata->phy_data;
392 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
395 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
397 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
400 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
402 	xgbe_phy_pcs_power_cycle(pdata);
405 	xgbe_phy_start_ratechange(pdata);
407 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_1000_RATE);
408 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_1000_WORD);
409 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_1000_PLL);
411 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
413 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
415 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
417 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
419 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
421 	XRXTX_IOWRITE(pdata, RXTX_REG22,
424 	xgbe_phy_complete_ratechange(pdata);
430 xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
432 	struct xgbe_phy_data *phy_data = pdata->phy_data;
436 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
452 xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
454 	struct xgbe_phy_data *phy_data = pdata->phy_data;
458 	if (xgbe_phy_cur_mode(pdata) == XGBE_MODE_KR) {
471 xgbe_phy_get_mode(struct xgbe_prv_data *pdata, int speed)
473 	struct xgbe_phy_data *phy_data = pdata->phy_data;
490 xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
494 		xgbe_phy_kx_1000_mode(pdata);
497 		xgbe_phy_kx_2500_mode(pdata);
500 		xgbe_phy_kr_mode(pdata);
508 xgbe_phy_get_type(struct xgbe_prv_data *pdata, struct ifmediareq * ifmr)
511 	switch (pdata->phy.speed) {
528 xgbe_phy_check_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode, bool advert)
531 	if (pdata->phy.autoneg == AUTONEG_ENABLE)
536 		cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
545 xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
550 		return (xgbe_phy_check_mode(pdata, mode,
551 		    XGBE_ADV(&pdata->phy, 1000baseKX_Full)));
553 		return (xgbe_phy_check_mode(pdata, mode,
554 		    XGBE_ADV(&pdata->phy, 2500baseX_Full)));
556 		return (xgbe_phy_check_mode(pdata, mode,
557 		    XGBE_ADV(&pdata->phy, 10000baseKR_Full)));
564 xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
566 	struct xgbe_phy_data *phy_data = pdata->phy_data;
585 xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
594 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
595 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
601 xgbe_phy_stop(struct xgbe_prv_data *pdata)
607 xgbe_phy_start(struct xgbe_prv_data *pdata)
614 xgbe_phy_reset(struct xgbe_prv_data *pdata)
619 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
621 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
626 		reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
636 xgbe_phy_exit(struct xgbe_prv_data *pdata)
642 xgbe_phy_init(struct xgbe_prv_data *pdata)
649 	XGBE_ZERO_SUP(&pdata->phy);
650 	XGBE_SET_SUP(&pdata->phy, Autoneg);
651 	XGBE_SET_SUP(&pdata->phy, Pause);
652 	XGBE_SET_SUP(&pdata->phy, Asym_Pause);
653 	XGBE_SET_SUP(&pdata->phy, Backplane);
654 	XGBE_SET_SUP(&pdata->phy, 10000baseKR_Full);
657 		XGBE_SET_SUP(&pdata->phy, 1000baseKX_Full);
660 		XGBE_SET_SUP(&pdata->phy, 2500baseX_Full);
664 	if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
665 		XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);
667 	pdata->phy_data = phy_data;