dev/amdsbwd/amdsbwd.c

140 pmio_write(struct resource *res, uint8_t reg, uint8_t val)
143 	bus_write_1(res, 1, val);	/* Data */
153 wdctrl_write(struct amdsbwd_softc *sc, uint32_t val)
155 	bus_write_4(sc->res_ctrl, 0, val);
165 wdcount_write(struct amdsbwd_softc *sc, uint32_t val)
167 	bus_write_4(sc->res_count, 0, val);
173 	uint32_t val;
175 	val = wdctrl_read(sc);
176 	val |= AMDSB_WD_RUN;
177 	wdctrl_write(sc, val);
185 	uint32_t val;
187 	val = wdctrl_read(sc);
188 	val &= ~AMDSB_WD_RUN;
189 	wdctrl_write(sc, val);
197 	uint32_t val;
199 	val = wdctrl_read(sc);
200 	val |= AMDSB_WD_RELOAD;
201 	wdctrl_write(sc, val);
282 	uint8_t	val;
286 	val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0);
287 	if (val != 0)
288 		amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val);
289 	val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1);
290 	if (val != 0)
291 		amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val);
292 	if ((val & AMDSB_WD_RST_STS) != 0)
303 	val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
304 	val &= ~AMDSB_WDT_RES_MASK;
305 	val |= AMDSB_WDT_RES_1S;
306 	pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
309 	val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
310 	val &= ~AMDSB_WDT_DISABLE;
311 	pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
323 	uint32_t	val;
328 	val = pmio_read(pmres, AMDSB8_PM_RESET_CTRL);
329 	if ((val & AMDSB8_RST_STS_DIS) != 0) {
330 		val &= ~AMDSB8_RST_STS_DIS;
331 		pmio_write(pmres, AMDSB8_PM_RESET_CTRL, val);
333 	val = 0;
335 		val <<= 8;
336 		val |= pmio_read(pmres, AMDSB8_PM_RESET_STATUS + i);
338 	if (val != 0)
339 		amdsbwd_verbose_printf(dev, "ResetStatus = 0x%08x\n", val);
340 	if ((val & AMDSB8_WD_RST_STS) != 0)
351 	val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
352 	val &= ~AMDSB8_WDT_RES_MASK;
353 	val |= AMDSB8_WDT_1HZ;
354 	pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val);
356 	val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
357 	amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#04x\n", val);
364 	val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
365 	val &= ~AMDSB8_WDT_DISABLE;
366 	val |= AMDSB8_WDT_DEC_EN;
367 	pmio_write(pmres, AMDSB8_PM_WDT_EN, val);
369 	val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
370 	device_printf(dev, "AMDSB8_PM_WDT_EN value = %#04x\n", val);
378 	uint8_t	val;
383 	val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
384 	val |= AMDFCH41_WDT_EN;
385 	pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val);
387 	val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0);
388 	device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n", val);
391 	val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL);
392 	if ((val & AMDFCH41_MMIO_EN) != 0) {
405 	val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
406 	val &= ~AMDFCH41_WDT_RES_MASK;
407 	val |= AMDFCH41_WDT_RES_1S;
408 	val &= ~AMDFCH41_WDT_EN_MASK;
409 	val |= AMDFCH41_WDT_ENABLE;
410 	pmio_write(pmres, AMDFCH41_PM_DECODE_EN3, val);
412 	val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3);
414 	    val);
570 	uint32_t val;
573 	val = wdctrl_read(sc);
574 	val &= ~AMDSB_WD_RUN;
575 	wdctrl_write(sc, val);