Lines Matching refs:v4
350 U32 v4 = seed - PRIME32_1;
356 v4 = XXH32_round(v4, XXH_get32bits(p)); p+=4;
359 h32 = XXH_rotl32(v1, 1) + XXH_rotl32(v2, 7) + XXH_rotl32(v3, 12) + XXH_rotl32(v4, 18);
450 U64 v4 = seed - PRIME64_1;
456 v4 = XXH64_round(v4, XXH_get64bits(p)); p+=8;
459 h64 = XXH_rotl64(v1, 1) + XXH_rotl64(v2, 7) + XXH_rotl64(v3, 12) + XXH_rotl64(v4, 18);
463 h64 = XXH64_mergeRound(h64, v4);
561 state.v4 = seed - PRIME32_1;
574 state.v4 = seed - PRIME64_1;
604 state->v4 = XXH32_round(state->v4, XXH_readLE32(p32, endian)); p32++;
615 U32 v4 = state->v4;
621 v4 = XXH32_round(v4, XXH_readLE32(p, endian)); p+=4;
627 state->v4 = v4;
657 h32 = XXH_rotl32(state->v1, 1) + XXH_rotl32(state->v2, 7) + XXH_rotl32(state->v3, 12) + XXH_rotl32(state->v4, 18);
724 state->v4 = XXH64_round(state->v4, XXH_readLE64(state->mem64+3, endian));
734 U64 v4 = state->v4;
740 v4 = XXH64_round(v4, XXH_readLE64(p, endian)); p+=8;
746 state->v4 = v4;
779 U64 const v4 = state->v4;
781 h64 = XXH_rotl64(v1, 1) + XXH_rotl64(v2, 7) + XXH_rotl64(v3, 12) + XXH_rotl64(v4, 18);
785 h64 = XXH64_mergeRound(h64, v4);