dev/rtw89/mac.c

650 	u32 dmac_err, imr, isr;
660 			imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR);
664 			    ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) {
3095 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3098 	rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set);
3103 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3105 	rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set);
3111 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3126 			  imr->mpdu_tx_imr_set);
3133 			  imr->mpdu_rx_imr_set);
3138 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3145 			  imr->sta_sch_imr_set);
3150 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3152 	rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg,
3153 			  imr->txpktctl_imr_b0_clr);
3154 	rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg,
3155 			  imr->txpktctl_imr_b0_set);
3156 	rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg,
3157 			  imr->txpktctl_imr_b1_clr);
3158 	rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg,
3159 			  imr->txpktctl_imr_b1_set);
3164 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3166 	rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr);
3167 	rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set);
3172 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3174 	rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr);
3175 	rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set);
3186 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3189 			  imr->host_disp_imr_clr);
3191 			  imr->host_disp_imr_set);
3193 			  imr->cpu_disp_imr_clr);
3195 			  imr->cpu_disp_imr_set);
3197 			  imr->other_disp_imr_clr);
3199 			  imr->other_disp_imr_set);
3210 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3212 	rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg,
3214 	rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3216 	rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3217 			  imr->bbrpt_err_imr_set);
3218 	rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg,
3235 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3239 	rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr);
3240 	rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set);
3245 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3249 	reg = rtw89_mac_reg_by_idx(imr->cdma_imr_0_reg, mac_idx);
3250 	rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr);
3251 	rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set);
3254 		reg = rtw89_mac_reg_by_idx(imr->cdma_imr_1_reg, mac_idx);
3255 		rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr);
3256 		rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set);
3262 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3265 	reg = rtw89_mac_reg_by_idx(imr->phy_intf_imr_reg, mac_idx);
3266 	rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr);
3267 	rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set);
3272 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3275 	reg = rtw89_mac_reg_by_idx(imr->rmac_imr_reg, mac_idx);
3276 	rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr);
3277 	rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set);
3282 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3285 	reg = rtw89_mac_reg_by_idx(imr->tmac_imr_reg, mac_idx);
3286 	rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr);
3287 	rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set);