mediatek/mt76/mt76x02_phy.c

12 void mt76x02_phy_set_rxpath(struct mt76x02_dev *dev)
16 	val = mt76_rr(dev, MT_BBP(AGC, 0));
19 	switch (dev->mphy.chainmask & 0xf) {
28 	mt76_wr(dev, MT_BBP(AGC, 0), val);
30 	val = mt76_rr(dev, MT_BBP(AGC, 0));
34 void mt76x02_phy_set_txdac(struct mt76x02_dev *dev)
38 	txpath = (dev->mphy.chainmask >> 8) & 0xf;
41 		mt76_set(dev, MT_BBP(TXBE, 5), 0x3);
44 		mt76_clear(dev, MT_BBP(TXBE, 5), 0x3);
93 void mt76x02_phy_set_txpower(struct mt76x02_dev *dev, int txp_0, int txp_1)
95 	struct mt76x02_rate_power *t = &dev->rate_power;
97 	mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, txp_0);
98 	mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, txp_1);
100 	mt76_wr(dev, MT_TX_PWR_CFG_0,
103 	mt76_wr(dev, MT_TX_PWR_CFG_1,
106 	mt76_wr(dev, MT_TX_PWR_CFG_2,
109 	mt76_wr(dev, MT_TX_PWR_CFG_3,
112 	mt76_wr(dev, MT_TX_PWR_CFG_4,
114 	mt76_wr(dev, MT_TX_PWR_CFG_7,
117 	mt76_wr(dev, MT_TX_PWR_CFG_8,
119 	mt76_wr(dev, MT_TX_PWR_CFG_9,
124 void mt76x02_phy_set_bw(struct mt76x02_dev *dev, int width, u8 ctrl)
143 	mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);
144 	mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val);
145 	mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl);
146 	mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl);
150 void mt76x02_phy_set_band(struct mt76x02_dev *dev, int band,
155 		mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
156 		mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
159 		mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
160 		mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
164 	mt76_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M,
169 bool mt76x02_phy_adjust_vga_gain(struct mt76x02_dev *dev)
171 	u8 limit = dev->cal.low_gain > 0 ? 16 : 4;
176 			      mt76_rr(dev, MT_RX_STAT_1));
177 	dev->cal.false_cca = false_cca;
178 	if (false_cca > 800 && dev->cal.agc_gain_adjust < limit) {
179 		dev->cal.agc_gain_adjust += 2;
181 	} else if ((false_cca < 10 && dev->cal.agc_gain_adjust > 0) ||
182 		   (dev->cal.agc_gain_adjust >= limit && false_cca < 500)) {
183 		dev->cal.agc_gain_adjust -= 2;
187 	dev->cal.agc_lowest_gain = dev->cal.agc_gain_adjust >= limit;
193 void mt76x02_init_agc_gain(struct mt76x02_dev *dev)
195 	dev->cal.agc_gain_init[0] = mt76_get_field(dev, MT_BBP(AGC, 8),
197 	dev->cal.agc_gain_init[1] = mt76_get_field(dev, MT_BBP(AGC, 9),
199 	memcpy(dev->cal.agc_gain_cur, dev->cal.agc_gain_init,
200 	       sizeof(dev->cal.agc_gain_cur));
201 	dev->cal.low_gain = -1;
202 	dev->cal.gain_init_done = true;