Lines Matching refs:dev
16 struct mt76x02_dev *dev = from_tasklet(dev, t, mt76.pre_tbtt_tasklet);
17 struct mt76_dev *mdev = &dev->mt76;
18 struct mt76_queue *q = dev->mphy.q_tx[MT_TXQ_PSD];
23 if (mt76_hw(dev)->conf.flags & IEEE80211_CONF_OFFCHANNEL)
26 mt76x02_resync_beacon_timer(dev);
29 mt76_set(dev, MT_BCN_BYPASS_MASK, 0xffff);
30 dev->beacon_data_count = 0;
32 ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev),
34 mt76x02_update_beacon_iter, dev);
36 mt76_wr(dev, MT_BCN_BYPASS_MASK,
37 0xff00 | ~(0xff00 >> dev->beacon_data_count));
44 mt76x02_enqueue_buffered_bc(dev, &data, 8);
62 mt76_tx_queue_skb(dev, q, MT_TXQ_PSD, skb, &mvif->group_wcid,
68 static void mt76x02e_pre_tbtt_enable(struct mt76x02_dev *dev, bool en)
71 tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
73 tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
76 static void mt76x02e_beacon_enable(struct mt76x02_dev *dev, bool en)
78 mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en);
80 mt76x02_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
82 mt76x02_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
85 void mt76x02e_init_beacon_config(struct mt76x02_dev *dev)
94 dev->beacon_ops = &beacon_ops;
97 mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT,
99 mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_GP_TIMER,
101 mt76_wr(dev, MT_INT_TIMER_EN, 0);
103 mt76x02_init_beacon_config(dev);
108 mt76x02_init_rx_queue(struct mt76x02_dev *dev, struct mt76_queue *q,
113 err = mt76_queue_alloc(dev, q, idx, n_desc, bufsize,
118 mt76x02_irq_enable(dev, MT_INT_RX_DONE(idx));
123 static void mt76x02_process_tx_status_fifo(struct mt76x02_dev *dev)
128 while (kfifo_get(&dev->txstatus_fifo, &stat))
129 mt76x02_send_tx_status(dev, &stat, &update);
134 struct mt76x02_dev *dev;
136 dev = container_of(w, struct mt76x02_dev, mt76.tx_worker);
138 mt76x02_mac_poll_tx_status(dev, false);
139 mt76x02_process_tx_status_fifo(dev);
141 mt76_txq_schedule_all(&dev->mphy);
146 struct mt76x02_dev *dev = container_of(napi, struct mt76x02_dev,
150 mt76x02_mac_poll_tx_status(dev, false);
152 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
154 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
157 mt76x02_irq_enable(dev, MT_INT_TX_DONE_ALL);
159 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
161 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
163 mt76_worker_schedule(&dev->mt76.tx_worker);
168 int mt76x02_dma_init(struct mt76x02_dev *dev)
178 status_fifo = devm_kzalloc(dev->mt76.dev, fifo_size, GFP_KERNEL);
182 dev->mt76.tx_worker.fn = mt76x02_tx_worker;
183 tasklet_setup(&dev->mt76.pre_tbtt_tasklet, mt76x02_pre_tbtt_tasklet);
185 spin_lock_init(&dev->txstatus_fifo_lock);
186 kfifo_init(&dev->txstatus_fifo, status_fifo, fifo_size);
188 mt76_dma_attach(&dev->mt76);
190 mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
193 ret = mt76_init_tx_queue(&dev->mphy, i, mt76_ac_to_hwq(i),
200 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT_TX_HW_QUEUE_MGMT,
205 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT_TX_HW_QUEUE_MCU,
210 mt76x02_irq_enable(dev,
218 ret = mt76x02_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
223 q = &dev->mt76.q_rx[MT_RXQ_MAIN];
225 ret = mt76x02_init_rx_queue(dev, q, 0, MT76X02_RX_RING_SIZE,
230 ret = mt76_init_queues(dev, mt76_dma_rx_poll);
234 netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
236 napi_enable(&dev->mt76.tx_napi);
244 struct mt76x02_dev *dev;
246 dev = container_of(mdev, struct mt76x02_dev, mt76);
247 mt76x02_irq_enable(dev, MT_INT_RX_DONE(q));
253 struct mt76x02_dev *dev = dev_instance;
256 intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
257 intr &= dev->mt76.mmio.irqmask;
258 mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
260 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
263 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
269 mt76x02_irq_disable(dev, mask);
272 napi_schedule(&dev->mt76.napi[0]);
275 napi_schedule(&dev->mt76.napi[1]);
278 tasklet_schedule(&dev->mt76.pre_tbtt_tasklet);
282 if (dev->mt76.csa_complete)
283 mt76_csa_finish(&dev->mt76);
285 mt76_queue_kick(dev, dev->mphy.q_tx[MT_TXQ_PSD]);
289 mt76x02_mac_poll_tx_status(dev, true);
292 napi_schedule(&dev->mt76.tx_napi);
295 tasklet_schedule(&dev->dfs_pd.dfs_tasklet);
301 static void mt76x02_dma_enable(struct mt76x02_dev *dev)
305 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
306 mt76x02_wait_for_wpdma(&dev->mt76, 1000);
312 mt76_set(dev, MT_WPDMA_GLO_CFG, val);
313 mt76_clear(dev, MT_WPDMA_GLO_CFG,
317 void mt76x02_dma_disable(struct mt76x02_dev *dev)
319 u32 val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
325 mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
329 void mt76x02_mac_start(struct mt76x02_dev *dev)
331 mt76x02_mac_reset_counters(dev);
332 mt76x02_dma_enable(dev);
333 mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter);
334 mt76_wr(dev, MT_MAC_SYS_CTRL,
337 mt76x02_irq_enable(dev,
343 static bool mt76x02_tx_hang(struct mt76x02_dev *dev)
350 q = dev->mphy.q_tx[i];
352 prev_dma_idx = dev->mt76.tx_dma_idx[i];
354 dev->mt76.tx_dma_idx[i] = dma_idx;
357 dev->tx_hang_check[i] = 0;
361 if (++dev->tx_hang_check[i] >= MT_TX_HANG_TH)
372 struct mt76x02_dev *dev = hw->priv;
383 mt76x02_mac_wcid_sync_pn(dev, wcid->idx, key);
386 static void mt76x02_reset_state(struct mt76x02_dev *dev)
390 lockdep_assert_held(&dev->mt76.mutex);
392 clear_bit(MT76_STATE_RUNNING, &dev->mphy.state);
395 ieee80211_iter_keys_rcu(dev->mt76.hw, NULL, mt76x02_key_sync, NULL);
405 wcid = rcu_dereference_protected(dev->mt76.wcid[i],
406 lockdep_is_held(&dev->mt76.mutex));
410 rcu_assign_pointer(dev->mt76.wcid[i], NULL);
418 __mt76_sta_remove(&dev->mt76, vif, sta);
422 dev->mt76.vif_mask = 0;
423 dev->mt76.beacon_mask = 0;
426 static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
428 u32 mask = dev->mt76.mmio.irqmask;
429 bool restart = dev->mt76.mcu_ops->mcu_restart;
432 ieee80211_stop_queues(dev->mt76.hw);
433 set_bit(MT76_RESET, &dev->mphy.state);
435 tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
436 mt76_worker_disable(&dev->mt76.tx_worker);
437 napi_disable(&dev->mt76.tx_napi);
439 mt76_for_each_q_rx(&dev->mt76, i) {
440 napi_disable(&dev->mt76.napi[i]);
443 mutex_lock(&dev->mt76.mutex);
445 dev->mcu_timeout = 0;
447 mt76x02_reset_state(dev);
449 if (dev->mt76.beacon_mask)
450 mt76_clear(dev, MT_BEACON_TIME_CFG,
454 mt76x02_irq_disable(dev, mask);
457 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
458 mt76_wr(dev, MT_MAC_SYS_CTRL, 0);
459 mt76_clear(dev, MT_WPDMA_GLO_CFG,
462 mt76_wr(dev, MT_INT_SOURCE_CSR, 0xffffffff);
465 mt76_set(dev, 0x734, 0x3);
468 mt76_mcu_restart(dev);
470 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true);
472 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
474 mt76_for_each_q_rx(&dev->mt76, i) {
475 mt76_queue_rx_reset(dev, i);
478 mt76_tx_status_check(&dev->mt76, true);
480 mt76x02_mac_start(dev);
482 if (dev->ed_monitor)
483 mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
485 if (dev->mt76.beacon_mask && !restart)
486 mt76_set(dev, MT_BEACON_TIME_CFG,
490 mt76x02_irq_enable(dev, mask);
492 mutex_unlock(&dev->mt76.mutex);
494 clear_bit(MT76_RESET, &dev->mphy.state);
496 mt76_worker_enable(&dev->mt76.tx_worker);
497 tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
500 napi_enable(&dev->mt76.tx_napi);
501 napi_schedule(&dev->mt76.tx_napi);
503 mt76_for_each_q_rx(&dev->mt76, i) {
504 napi_enable(&dev->mt76.napi[i]);
505 napi_schedule(&dev->mt76.napi[i]);
510 set_bit(MT76_RESTART, &dev->mphy.state);
511 mt76x02_mcu_function_select(dev, Q_SELECT, 1);
512 ieee80211_restart_hw(dev->mt76.hw);
514 ieee80211_wake_queues(dev->mt76.hw);
515 mt76_txq_schedule_all(&dev->mphy);
522 struct mt76x02_dev *dev = hw->priv;
527 clear_bit(MT76_RESTART, &dev->mphy.state);
531 static void mt76x02_check_tx_hang(struct mt76x02_dev *dev)
533 if (test_bit(MT76_RESTART, &dev->mphy.state))
536 if (!mt76x02_tx_hang(dev) && !dev->mcu_timeout)
539 mt76x02_watchdog_reset(dev);
541 dev->tx_hang_reset++;
542 memset(dev->tx_hang_check, 0, sizeof(dev->tx_hang_check));
543 memset(dev->mt76.tx_dma_idx, 0xff,
544 sizeof(dev->mt76.tx_dma_idx));
549 struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev,
552 mt76x02_check_tx_hang(dev);
554 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->wdt_work,