athk/ath10k/pci.c

809 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
811 	struct ath10k *ar = pipe->hif_ce_state;
813 	struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
818 	skb = dev_alloc_skb(pipe->buf_sz);
848 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
850 	struct ath10k *ar = pipe->hif_ce_state;
853 	struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
856 	if (pipe->buf_sz == 0)
867 		ret = __ath10k_pci_rx_post_buf(pipe);
1282 		ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1331 		ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1358 	/* CE4 polling needs to be done whenever CE pipe which transports
1401 	/* CE4 polling needs to be done whenever CE pipe which transports
1500 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
1506 	return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
1875 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
1891 		resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
1897 		if (resources > (ar_pci->attr[pipe].src_nentries >> 1))
1900 	ath10k_ce_per_engine_service(ar, pipe);
1959 	ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
2451 		ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
2457 		ath10k_err(ar, "Invalid pipe cfg addr\n");
2467 		ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
2476 		ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
2490 		ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
2583 	struct ath10k_pci_pipe *pipe;
2588 		pipe = &ar_pci->pipe_info[i];
2589 		pipe->ce_hdl = &ce->ce_states[i];
2590 		pipe->pipe_num = i;
2591 		pipe->hif_ce_state = ar;
2595 			ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
2602 			ar_pci->ce_diag = pipe->ce_hdl;
2606 		pipe->buf_sz = (size_t)(ar_pci->attr[i].src_sz_max);
2628 			ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",