dtrace/x86/dis_tables.c

86 	uint_t		it_invalid64:1;		/* opcode invalid in amd64 */
283 #define	MODE_IMPLIED	3	/* constant value implied from opcode */
290  *   "T" - means to Terminate indirections (this is the final opcode)
295  *   "NS" - means "no suffix" which is the operand length suffix of the opcode
297  *   "u" - means the opcode is invalid in IA32 but valid in amd64
298  *   "x" - means the opcode is invalid in amd64, but not IA32
558  *	"decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
627  *	Decode table for 0x0FC7 opcode (group 9)
637  *	Decode table for 0x0FC7 opcode (group 9) mode 3
647  *	Decode table for 0x0FC7 opcode with 0x66 prefix
657  *	Decode table for 0x0FC7 opcode with 0xF3 prefix
667  *	Decode table for 0x0FC8 opcode -- 486 bswap instruction
2840 #define	REX_B 0x01	/* extends ModRM r_m, SIB base, or opcode reg */
2858 #define	VEX_W 0x08	/* opcode specific, use like REX.W */
2862 #define	VEX_p 0x03	/* VEX pp field, opcode extension */
2865 #define	VEX_m_0F 0x01   /* implied 0F leading opcode byte */
2866 #define	VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */
2867 #define	VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */
2917  *	[opcode - 0x90][VEX_W][VEX_L].
3343 	uint_t ss;		/* scale-factor from opcode */
3562  * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r")
3587  *	0 for "opcode imm, r, r_m" or
3588  *	1 for "opcode imm, r_m, r"
3627  * returns non-zero for bad opcode
3644 	uint_t wbit;		/* opcode wbit, 0 is 8 bit, !0 for opnd_size */
3653 	uint_t opcode3;		/* extra opcode bits usually from ModRM byte */
3752 	 * Get one opcode byte and check for zero padding that follows
3881 		/* Reuse opcode1 & opcode2 to get the real opcode now */
4137 	 * Some 386 instructions have 2 bytes of opcode before the mod_r/m
4199 			 * Both crc32 and movbe have the same 3rd opcode
4331 	 * In amd64 bit mode, ARPL opcode is changed to MOVSXD
4339 	 * at this point we should have a correct (or invalid) opcode
4541 	 * At this point most instructions can format the opcode mnemonic
4716 	 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s)
4791 		 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83
5166 		/* long seg reg from opcode */
5639 	 * byte (format Ib).  The int 3 instruction (opcode 0xCC),
5641 	 * it is implied by the opcode. It must be converted
5755 		 * XRSTOR, XSAVEOPT and LFENCE share the same opcode but
6486 isunsigned_op(char *opcode)
6496 	where = opcode + strlen(opcode) - 1;
6497 	while (where > opcode && *where != ' ')