Lines Matching defs:wval

652     uint64_t wval, void *arg)
1011 uint64_t wval, void *arg)
1029 wval &= GICD_CTLR_G1A;
1030 wval |= GICD_CTLR_ARE_NS;
1032 vgic->gicd_ctlr = wval;
1062 u_int size, uint64_t wval, void *arg)
1068 irqid = wval & GICD_SPI_INTID_MASK;
1087 uint64_t wval, void *arg)
1096 write_enabler(hypctx, n, true, wval);
1113 uint64_t wval, void *arg)
1122 write_enabler(hypctx, n, false, wval);
1139 uint64_t wval, void *arg)
1148 write_pendr(hypctx, n, true, wval);
1165 uint64_t wval, void *arg)
1174 write_pendr(hypctx, n, false, wval);
1192 uint64_t wval, void *arg)
1201 write_activer(hypctx, n, true, wval);
1219 uint64_t wval, void *arg)
1228 write_activer(hypctx, n, false, wval);
1247 u_int size, uint64_t wval, void *arg)
1254 write_priorityr(hypctx, irq_base, size, wval);
1271 uint64_t wval, void *arg)
1280 write_config(hypctx, n, wval);
1297 uint64_t wval, void *arg)
1304 write_route(hypctx, n, wval, offset, size);
1344 u_int reg_list_size, u_int reg, u_int size, uint64_t wval, void *arg)
1354 size, wval, NULL);
1407 dist_write(struct vcpu *vcpu, uint64_t fault_ipa, uint64_t wval,
1433 reg, size, wval, NULL))
1507 u_int size, uint64_t wval, void *arg)
1511 write_enabler(hypctx, 0, true, wval);
1517 u_int size, uint64_t wval, void *arg)
1521 write_enabler(hypctx, 0, false, wval);
1534 u_int size, uint64_t wval, void *arg)
1538 write_pendr(hypctx, 0, true, wval);
1544 u_int size, uint64_t wval, void *arg)
1548 write_pendr(hypctx, 0, false, wval);
1561 u_int size, uint64_t wval, void *arg)
1563 write_activer(hypctx, 0, true, wval);
1569 u_int size, uint64_t wval, void *arg)
1571 write_activer(hypctx, 0, false, wval);
1587 u_int size, uint64_t wval, void *arg)
1592 write_priorityr(hypctx, irq_base, size, wval);
1604 uint64_t wval, void *arg)
1608 write_config(hypctx, 1, wval);
1690 redist_write(struct vcpu *vcpu, uint64_t fault_ipa, uint64_t wval,
1750 nitems(redist_rd_registers), reg, size, wval, NULL))
1755 wval, NULL))