nvidia/tegra124/tegra124_clk_pll.c

385     uint64_t *fout, int flags, int *stop);
701 pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags,
718 		    (*fout != (((fin / m) * n) /p)))
721 		*fout = ((fin / m) * n) /p;
760 	*fout = ((fin / m) * n) / p;
765 plla_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
771 	n = (*fout * p * m + fin / 2)/ fin;
773 	return (pll_set_std(sc,  fin, fout, flags, m, n, p));
777 pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
783 	n = (*fout * p * m + fin / 2)/ fin;
785 	return (pll_set_std( sc, fin, fout, flags, m, n, p));
803 plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
821 		vco = *fout * p;
828 			n = (*fout * p * m + fin / 2) / fin;
843 			err = *fout - vco / p;
861 	if (best_err > ((*fout * 100) / 4))
866 	rv = pll_set_std(sc, fin, fout, flags, best_m, best_n, best_p);
872 pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
878 	n = *fout * p * m / fin;
880 	return (pll_set_std(sc, fin, fout, flags, m, n, p));
884 pllx_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
895 	n = (*fout * p * m + fin / 2)/ fin;
907 		    (*fout != (((fin / m) * n) /p)))
909 		*fout = ((fin / m) * n) /p;
948 	*fout = ((fin / m) * n) / p;
953 tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout,
962 	   clknode_get_name(clknode), *fout, fin);
965 		rv = plla_set_freq(sc, fin, fout, flags);
968 		rv = pllc_set_freq(sc, fin, fout, flags);
971 		rv = plld2_set_freq(sc, fin, fout, flags);
975 		rv = pllrefe_set_freq(sc, fin, fout, flags);
979 		rv = pllx_set_freq(sc, fin, fout, flags);
983 		if (*fout == 480000000)  /* PLLU is fixed to 480 MHz */