vmm/io/vhpet.c

92 	} timer[VHPET_NUM_TIMERS];
109 	cap &= ~HPET_CAP_COUNT_SIZE;		/* 32-bit timer */
129 	if ((vhpet->timer[n].cap_config & msi_enable) == msi_enable)
139 	 * If the timer is configured to use MSI then treat it as if the
140 	 * timer is not connected to the ioapic.
145 	return ((vhpet->timer[n].cap_config & HPET_TCNF_INT_ROUTE) >> 9);
181 		KASSERT(pin != 0, ("vhpet timer %d irq incorrectly routed", n));
191 	return ((vhpet->timer[n].cap_config & HPET_TCNF_TYPE) != 0);
198 	return ((vhpet->timer[n].cap_config & HPET_TCNF_INT_ENB) != 0);
206 	    "timer %d is using MSI", n));
208 	if ((vhpet->timer[n].cap_config & HPET_TCNF_INT_TYPE) == 0)
219 	/* If interrupts are not enabled for this timer then just return. */
232 		lapic_intr_msi(vhpet->vm, vhpet->timer[n].msireg >> 32,
233 		    vhpet->timer[n].msireg & 0xffffffff);
256 	KASSERT(vhpet->timer[n].comprate != 0, ("hpet t%d is not periodic", n));
258 	compval = vhpet->timer[n].compval;
259 	comprate = vhpet->timer[n].comprate;
274 	vhpet->timer[n].compval = compnext;
290 	callout = &vhpet->timer[n].callout;
320 	callout_stop(&vhpet->timer[n].callout);
324 	 * had a chance to execute yet then trigger the timer interrupt
325 	 * here. Failing to do so will result in a missed timer interrupt
329 	if (vhpet->timer[n].callout_sbt < now) {
331 		    "stopping timer", n);
341 	if (vhpet->timer[n].comprate != 0)
352 	delta = (vhpet->timer[n].compval - counter) * vhpet->freq_sbt;
354 	vhpet->timer[n].callout_sbt = now + delta;
355 	callout_reset_sbt(&vhpet->timer[n].callout, vhpet->timer[n].callout_sbt,
356 	    precision, vhpet_handler, &vhpet->timer[n].arg, C_ABSOLUTE);
405 			panic("vhpet timer %d isr should not be asserted", n);
408 	oldval = vhpet->timer[n].cap_config;
418 	vhpet->timer[n].cap_config = newval;
426 	allowed_irqs = vhpet->timer[n].cap_config >> 32;
432 		vhpet->timer[n].cap_config &= ~HPET_TCNF_INT_ROUTE;
436 		vhpet->timer[n].comprate = 0;
439 	 * If the timer's ISR bit is set then clear it in the following cases:
444 	 * This is to ensure that this timer's level triggered interrupt does
448 		KASSERT(old_pin != 0, ("timer %d isr asserted to ioapic pin %d",
572 			old_compval = vhpet->timer[i].compval;
573 			old_comprate = vhpet->timer[i].comprate;
581 				val64 = vhpet->timer[i].comprate;
583 				vhpet->timer[i].comprate = val64;
584 				if ((vhpet->timer[i].cap_config &
586 					vhpet->timer[i].compval = val64;
589 				KASSERT(vhpet->timer[i].comprate == 0,
590 				    ("vhpet one-shot timer %d has invalid "
591 				    "rate %u", i, vhpet->timer[i].comprate));
592 				val64 = vhpet->timer[i].compval;
594 				vhpet->timer[i].compval = val64;
596 			vhpet->timer[i].cap_config &= ~HPET_TCNF_VAL_SET;
598 			if (vhpet->timer[i].compval != old_compval ||
599 			    vhpet->timer[i].comprate != old_comprate) {
611 			update_register(&vhpet->timer[i].msireg, data, mask);
672 			data = vhpet->timer[i].cap_config;
678 			data = vhpet->timer[i].compval;
684 			data = vhpet->timer[i].msireg;
727 	 * Initialize HPET timer hardware state.
730 		vhpet->timer[i].cap_config = allowed_irqs << 32;
731 		vhpet->timer[i].cap_config |= HPET_TCAP_PER_INT;
732 		vhpet->timer[i].cap_config |= HPET_TCAP_FSB_INT_DEL;
734 		vhpet->timer[i].compval = 0xffffffff;
735 		callout_init(&vhpet->timer[i].callout, 1);
737 		arg = &vhpet->timer[i].arg;
751 		callout_drain(&vhpet->timer[i].callout);
787 	for (i = 0; i < nitems(vhpet->timer); i++) {
788 		SNAPSHOT_VAR_OR_LEAVE(vhpet->timer[i].cap_config,
790 		SNAPSHOT_VAR_OR_LEAVE(vhpet->timer[i].msireg, meta, ret, done);
791 		SNAPSHOT_VAR_OR_LEAVE(vhpet->timer[i].compval, meta, ret, done);
792 		SNAPSHOT_VAR_OR_LEAVE(vhpet->timer[i].comprate, meta, ret, done);
793 		SNAPSHOT_VAR_OR_LEAVE(vhpet->timer[i].callout_sbt,