vmm/amd/amdvi_priv.h

74 	uint8_t	 pt_level:3;		/* Paging level, 0 to disable. */
76 	uint8_t  :3;			/* Reserved[54:52] */
77 	uint8_t	 gv_valid:1;		/* Revision 2, GVA to SPA. */
78 	uint8_t	 gv_level:2;		/* Revision 2, GLX level. */
79 	uint8_t	 gv_cr3_lsb:3;		/* Revision 2, GCR3[14:12] */
80 	uint8_t	 read_allow:1;		/* I/O read enabled. */
81 	uint8_t	 write_allow:1;		/* I/O write enabled. */
82 	uint8_t  :1;			/* Reserved[63] */
85 	uint8_t	 iotlb_enable:1;	/* Device support IOTLB */
86 	uint8_t	 sup_second_io_fault:1;	/* Suppress subsequent I/O faults. */
87 	uint8_t	 sup_all_io_fault:1;	/* Suppress all I/O page faults. */
88 	uint8_t	 IOctl:2;		/* Port I/O control. */
89 	uint8_t	 iotlb_cache_disable:1;	/* IOTLB cache hints. */
90 	uint8_t	 snoop_disable:1;	/* Snoop disable. */
91 	uint8_t	 allow_ex:1;		/* Allow exclusion. */
92 	uint8_t	 sysmgmt:2;		/* System management message.*/
93 	uint8_t  :1;			/* Reserved[106] */
95 	uint8_t	 intmap_valid:1;	/* Interrupt map valid. */
96 	uint8_t	 intmap_len:4;		/* Interrupt map table length. */
97 	uint8_t	 intmap_ign:1;		/* Ignore unmapped interrupts. */
99 	uint8_t  :4;			/* Reserved[183:180] */
100 	uint8_t	 init_pass:1;		/* INIT pass through or PT */
101 	uint8_t	 extintr_pass:1;	/* External Interrupt PT */
102 	uint8_t	 nmi_pass:1;		/* NMI PT */
103 	uint8_t  :1;			/* Reserved[187] */
104 	uint8_t	 intr_ctrl:2;		/* Interrupt control */
105 	uint8_t	 lint0_pass:1;		/* LINT0 PT */
106 	uint8_t	 lint1_pass:1;		/* LINT1 PT */
117 	uint8_t		opcode:4;
158 	uint8_t		opcode:4;
191 		uint8_t  :4;
192 		uint8_t	 len:4;
193 		uint8_t  :4;
198 		uint8_t  :4;
199 		uint8_t	 len:4;
200 		uint8_t  :4;
205 		uint8_t	 enable:1;
206 		uint8_t	 allow:1;
221 		uint8_t  :4;
222 		uint8_t	 len:4;
223 		uint8_t  :4;
229 	uint8_t	 pad1[0x1FA8];		/* Padding. */
241 	uint8_t  :4;
244 	uint8_t  :4;
247 	uint8_t	 pad3[0x1FC0];		/* Padding. */
348 	uint8_t	 data;			/* Device configuration. */
393 	uint8_t		pci_cap;	/* PCI capability. */