Lines Matching refs:sq
354 struct t4_sq sq;
408 return wq->sq.in_use == 0;
413 return wq->sq.in_use == (wq->sq.size - 1);
418 return wq->sq.size - 1 - wq->sq.in_use;
423 return wq->sq.flags & T4_SQ_ONCHIP;
428 wq->sq.in_use++;
429 if (++wq->sq.pidx == wq->sq.size)
430 wq->sq.pidx = 0;
431 wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
432 if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
433 wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
437 wq->sq.queue[wq->sq.size].status.host_pidx = (wq->sq.pidx);
443 assert(wq->sq.in_use >= 1);
444 if (wq->sq.cidx == wq->sq.flush_cidx)
445 wq->sq.flush_cidx = -1;
446 wq->sq.in_use--;
447 if (++wq->sq.cidx == wq->sq.size)
448 wq->sq.cidx = 0;
449 assert((wq->sq.cidx != wq->sq.pidx) || wq->sq.in_use == 0);
453 wq->sq.queue[wq->sq.size].status.host_cidx = wq->sq.cidx;
481 if (t5_en_wc && inc == 1 && wq->sq.wc_reg_available) {
482 PDBG("%s: WC wq->sq.pidx = %d; len16=%d\n",
483 __func__, wq->sq.pidx, len16);
484 copy_wqe_to_udb(wq->sq.udb + 14, wqe);
486 PDBG("%s: DB wq->sq.pidx = %d; len16=%d\n",
487 __func__, wq->sq.pidx, len16);
488 writel(QID_V(wq->sq.bar2_qid) | PIDX_T5_V(inc),
489 wq->sq.udb);
503 *(volatile u32 *)&wq->sq.queue[wq->sq.size].flits[2+i] = i;
517 *(u32 *)&wq->sq.queue[wq->sq.size].flits[2] = i;
522 writel(QID_V(wq->sq.qid & wq->qid_mask) | PIDX_V(inc), wq->sq.udb);
530 if (t5_en_wc && inc == 1 && wq->sq.wc_reg_available) {