Lines Matching refs:XCore

1 //===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===//
9 // This file contains the XCore implementation of the MRegisterInfo class.
14 #include "XCore.h"
44 : XCoreGenRegisterInfo(XCore::LR) {
69 case XCore::LDWFI:
70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
75 case XCore::STWFI:
76 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
82 case XCore::LDAWFI:
83 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
101 RS->scavengeRegisterBackwards(XCore::GRRegsRegClass, II, false, 0);
106 case XCore::LDWFI:
107 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
112 case XCore::STWFI:
113 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
119 case XCore::LDAWFI:
120 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
139 case XCore::LDWFI:
140 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
145 case XCore::STWFI:
146 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
152 case XCore::LDAWFI:
153 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
172 if (OpCode==XCore::STWFI) {
174 RS->scavengeRegisterBackwards(XCore::GRRegsRegClass, II, false, 0);
178 BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0);
180 RS->scavengeRegisterBackwards(XCore::GRRegsRegClass, II, false, 0);
185 case XCore::LDWFI:
186 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
191 case XCore::STWFI:
192 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
198 case XCore::LDAWFI:
199 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
217 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
218 XCore::R8, XCore::R9, XCore::R10,
222 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
223 XCore::R8, XCore::R9,
236 Reserved.set(XCore::CP);
237 Reserved.set(XCore::DP);
238 Reserved.set(XCore::SP);
239 Reserved.set(XCore::LR);
241 Reserved.set(XCore::R10);
303 assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
326 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;