Target/RISCV/RISCVInsertVSETVLI.cpp

437     Register AVLReg;
471     AVLReg = Reg;
484     return AVLReg;
706       OS << "AVLReg=" << (unsigned)AVLReg;
801     Register AVLReg = MI.getOperand(1).getReg();
802     assert((AVLReg != RISCV::X0 || MI.getOperand(0).getReg() != RISCV::X0) &&
804     NewInfo.setAVLReg(AVLReg);
960   Register AVLReg = Info.getAVLReg();
961   if (AVLReg == RISCV::NoRegister) {
981   if (AVLReg.isVirtual())
982     MRI->constrainRegClass(AVLReg, &RISCV::GPRNoX0RegClass);
984   // Use X0 as the DestReg unless AVLReg is X0. We also need to change the
985   // opcode if the AVLReg is X0 as they have different register classes for
989   if (AVLReg == RISCV::X0) {
995       .addReg(AVLReg)
1246   Register AVLReg = Require.getAVLReg();
1247   if (!AVLReg.isVirtual())
1251   MachineInstr *PHI = MRI->getVRegDef(AVLReg);