Target/RISCV/RISCVISelLowering.cpp

165       // Disable the smallest fractional LMUL types if ELEN is less than
1454   // The maximum VF is for the smallest element width with LMUL=8.
2290     llvm_unreachable("Invalid LMUL.");
2311     llvm_unreachable("Invalid LMUL.");
2327   RISCVII::VLMUL LMUL = getLMUL(VT);
2328   if (LMUL == RISCVII::VLMUL::LMUL_F8 ||
2329       LMUL == RISCVII::VLMUL::LMUL_F4 ||
2330       LMUL == RISCVII::VLMUL::LMUL_F2 ||
2331       LMUL == RISCVII::VLMUL::LMUL_1) {
2336   if (LMUL == RISCVII::VLMUL::LMUL_2) {
2341   if (LMUL == RISCVII::VLMUL::LMUL_4) {
2371   // LMUL>1 register class down to the outgoing one. At each step we half
2372   // the LMUL:
2533     // We prefer to use LMUL=1 for VLEN sized types. Use fractional lmuls for
2534     // narrower types. The smallest fractional LMUL we support is 8/ELEN. Within
2535     // each fractional LMUL we support SEW between 8 and LMUL*ELEN.
2704 /// is generally quadratic in the number of vreg implied by LMUL.  Note that
2711 /// vrgather.vi/vx may be linear in the number of vregs implied by LMUL,
2719 /// variants.)  Slides may be linear in the number of vregs implied by LMUL,
2727 /// variants.)  Slides may be linear in the number of vregs implied by LMUL,
3726   // Our main goal here is to reduce LMUL (and thus work) required to
3842   // being (at least) linear in LMUL.  As a result, using the vslidedown
3843   // lowering for every element ends up being VL*LMUL..
4973     // may involve vector splitting if we're already at LMUL=8, or our
4974     // user-supplied maximum fixed-length LMUL.
5027   // requires less work and less register pressure at high LMUL, and creates
7623   // the LMUL will be sufficient to hold the smaller type.
7875 // smallest subvector that the index fits in. This can be used to reduce LMUL
7931   // we're performing the scalar inserts and slideup on a smaller LMUL.
7937     // Do we know an upper bound on LMUL?
8176   // Reduce the LMUL of our slidedown and vmv.x.s to the smallest LMUL which
8196   // is linear in LMUL, performing N extracts using vslidedown becomes
8198   // seems to have the same problem (the store is linear in LMUL), but the
8324         SDValue LMUL = DAG.getConstant(Lmul, DL, XLenVT);
8330                             LMUL);
8339       SDValue LMUL = DAG.getConstant(Lmul, DL, XLenVT);
8347                                SEW, LMUL);
8412 // fractional LMULs. The LMUL is choosen so that with SEW=8 the VLMax is
8415 // SEW and LMUL are better for the surrounding vector instructions.
8420   // The smallest LMUL is only valid for the smallest element width.
8423   // Determine the VF that corresponds to LMUL 1 for ElementWidth.
8473 // LMUL * VLEN should be greater than or equal to EGS * SEW
9393   // LMUL group contains the specific subvector as we only know the minimum
9460   // lowering to an EXTRACT_SUBVECTOR grabbing the nearest LMUL=1 vector type
9463   // LMUL=1 type back into the larger vector (resolving to another subregister
9464   // operation). See below for how our VSLIDEUP works. We go via a LMUL=1 type
9575   // LMUL group contains the specific subvector as we only know the minimum
9585     // Shrink down Vec so we're performing the slidedown on a smaller LMUL.
9621   // Else SubVecVT is a fractional LMUL and may need to be slid down.
9624   // If the vector type is an LMUL-group type, extract a subvector equal to the
9628     // If VecVT has an LMUL > 1, then SubVecVT should have a smaller LMUL, and
9698   // If the VT is LMUL=8, we need to split and reassemble.
9777   // If the VT is LMUL=8, we need to split and reassemble.
9882 // TODO: This code assumes VLMAX <= 65536 for LMUL=8 SEW=16.
9907     // If this is LMUL=8, we have to split before can use vrgatherei16.vv.
9926     // Just promote the int type to i16 which will double the LMUL.
10886   // NOTE: This code assumes VLMAX <= 65536 for LMUL=8 SEW=16.
10888     // If this is LMUL=8, we have to split before using vrgatherei16.vv.
10931     // Just promote the int type to i16 which will double the LMUL.
12886   // work and less register pressure at high LMUL, and creates smaller constants
19810   // operations to correspond roughly to that threshold.  LMUL>1 operations
19813   // combining will typically form larger LMUL operations from the LMUL1
20004   auto [LMUL, Fractional] = RISCVVType::decodeVLMUL(getLMUL(ContainerVT));
20007   return Factor * LMUL <= 8;