Lines Matching refs:SP
1424 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP)
1425 .addReg(ARM::SP)
1477 .addReg(ARM::SP)
1503 .addReg(ARM::SP)
1511 .addReg(ARM::SP)
1515 .addReg(ARM::SP)
1521 .addReg(ARM::SP)
1530 .addReg(ARM::SP)
1564 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP)
1565 .addReg(ARM::SP)
1571 .addReg(ARM::SP)
1580 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTMSDB_UPD), ARM::SP)
1581 .addReg(ARM::SP)
1590 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTR_FPCXTS_pre), ARM::SP)
1591 .addReg(ARM::SP)
1666 .addReg(ARM::SP)
1672 .addReg(ARM::SP)
1680 .addReg(ARM::SP)
1731 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP)
1732 .addReg(ARM::SP)
1762 .addReg(ARM::SP)
1766 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP)
1767 .addReg(ARM::SP)
1773 ARM::SP)
1774 .addReg(ARM::SP)
1780 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDMSIA_UPD), ARM::SP)
1781 .addReg(ARM::SP)
2078 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2STMDB_UPD), ARM::SP)
2079 .addReg(ARM::SP)
2108 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2LDMIA_UPD), ARM::SP)
2109 .addReg(ARM::SP)
2266 TII->get(ARM::VLDR_FPCXTNS_post), ARM::SP)
2267 .addReg(ARM::SP)
3176 .addReg(ARM::SP, RegState::Define)
3177 .addReg(ARM::SP)