Lines Matching defs:UseMI
3311 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
3336 const MCInstrDesc &UseMCID = UseMI.getDesc();
3339 if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR)
3345 unsigned UseOpc = UseMI.getOpcode();
3360 Commute = UseMI.getOperand(2).getReg() != Reg;
3430 Register Reg1 = UseMI.getOperand(OpIdx).getReg();
3431 bool isKill = UseMI.getOperand(OpIdx).isKill();
3434 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc),
3440 UseMI.setDesc(get(NewUseOpc));
3441 UseMI.getOperand(1).setReg(NewReg);
3442 UseMI.getOperand(1).setIsKill();
3443 UseMI.getOperand(2).ChangeToImmediate(SOImmValV2);
3449 // For now, we fix the UseMI operand explicitly here:
3455 MRI->constrainRegClass(UseMI.getOperand(0).getReg(), TRC);
4364 unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {
4382 const MachineInstr *ResolvedUseMI = &UseMI;
4384 if (UseMI.isBundle()) {
4386 getBundledUseMI(&getRegisterInfo(), UseMI, Reg, UseIdx, UseAdj);
4399 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
4408 if (UseMI.isBranch())
4427 if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit())
4433 unsigned UseAlign = UseMI.hasOneMemOperand()
4434 ? (*UseMI.memoperands_begin())->getAlign().value()
4807 const MachineInstr &UseMI,
4810 unsigned UDomain = UseMI.getDesc().TSFlags & ARMII::DomainMask;
4817 SchedModel.computeOperandLatency(&DefMI, DefIdx, &UseMI, UseIdx);