lib/CodeGen/RegisterCoalescer.cpp

883     MachineInstr *UseMI = MO.getParent();
884     unsigned OpNo = &MO - &UseMI->getOperand(0);
885     SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI);
890     if (UseMI->isRegTiedToDefOperand(OpNo))
928     MachineInstr *UseMI = UseMO.getParent();
929     if (UseMI->isDebugInstr()) {
935     SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true);
946     if (UseMI == CopyMI)
948     if (!UseMI->isCopy())
950     if (UseMI->getOperand(0).getReg() != IntB.reg() ||
951         UseMI->getOperand(0).getSubReg())
960     LLVM_DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
972     deleteInstr(UseMI);
1636       MachineInstr *UseMI = UseMO.getParent();
1637       if (UseMI->isDebugInstr()) {
1644         MBB->splice(std::next(NewMI.getIterator()), UseMI->getParent(), UseMI);
1645         LLVM_DEBUG(dbgs() << "\t\tupdated: " << *UseMI);
1838     MachineInstr *UseMI = &*(I++);
1842     // the UseMI operands removes them from the SrcReg use-def chain, but when
1843     // SrcReg is DstReg we could encounter UseMI twice if it has multiple
1845     if (SrcReg == DstReg && !Visited.insert(UseMI).second)
1850     std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
1854     if (DstInt && !Reads && SubIdx && !UseMI->isDebugInstr())
1855       Reads = DstInt->liveAt(LIS->getInstructionIndex(*UseMI));
1857     // Replace SrcReg with DstReg in all UseMI operands.
1859       MachineOperand &MO = UseMI->getOperand(Ops[i]);
1884           SlotIndex MIIdx = UseMI->isDebugInstr()
1885             ? LIS->getSlotIndexes()->getIndexBefore(*UseMI)
1886             : LIS->getInstructionIndex(*UseMI);
1900       if (!UseMI->isDebugInstr())
1901         dbgs() << LIS->getInstructionIndex(*UseMI) << "\t";
1902       dbgs() << *UseMI;