lib/CodeGen/RegAllocGreedy.cpp

262   ExtraInfo->LRE_DidCloneVirtReg(New, Old);
292   auto Stage = ExtraInfo->getOrInitStage(Reg);
295     ExtraInfo->setStage(Reg, Stage);
489   unsigned Cascade = ExtraInfo->getOrAssignNewCascade(VirtReg.reg());
513     assert((ExtraInfo->getCascade(Intf->reg()) < Cascade ||
516     ExtraInfo->setCascade(Intf->reg(), Cascade);
1032     if (ExtraInfo->getOrInitStage(Reg.reg()) != RS_New)
1038       ExtraInfo->setStage(Reg, RS_Spill);
1049         ExtraInfo->setStage(Reg, RS_Split2);
1244   if (ExtraInfo->getStage(VirtReg) >= RS_Split2)
1323     if (ExtraInfo->getOrInitStage(LI.reg()) == RS_New && IntvMap[I] == 0)
1324       ExtraInfo->setStage(LI, RS_Spill);
1478   ExtraInfo->setStage(LREdit.begin(), LREdit.end(), RS_Spill);
1647   bool ProgressRequired = ExtraInfo->getStage(VirtReg) >= RS_Split2;
1783         ExtraInfo->setStage(LIS->getInterval(LREdit.get(I)), RS_Split2);
1804   if (ExtraInfo->getStage(VirtReg) >= RS_Spill)
1826   if (ExtraInfo->getStage(VirtReg) < RS_Split2) {
1897       if (((ExtraInfo->getStage(*Intf) == RS_Done &&
1970   assert((ExtraInfo->getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) &&
2179   if (ExtraInfo->getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) {
2191   if (ExtraInfo->getStage(VirtReg) < RS_Split) {
2439   LiveRangeStage Stage = ExtraInfo->getStage(VirtReg);
2441                     << ExtraInfo->getCascade(VirtReg.reg()) << '\n');
2467     ExtraInfo->setStage(VirtReg, RS_Split);
2491       ExtraInfo->getStage(VirtReg) < RS_Memory) {
2496     ExtraInfo->setStage(VirtReg, RS_Memory);
2504     ExtraInfo->setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done);
2751   ExtraInfo.emplace();