powerpc/powermac/cpcht.c

82 			    int *irq);
84 			    int irq);
86 			    int irq, uint64_t *addr, uint32_t *data);
198 	mtx_init(&sc->htirq_mtx, "cpcht irq", NULL, MTX_DEF);
217 	int i, nirq, irq;
276 			irq = PCIB_READ_CONFIG(dev, b, s, f, ptr + 4, 4);
282 			    irq | HTAPIC_MASK, 4);
283 			irq = (irq >> 16) & 0xff;
285 			sc->htirq_map[irq].irq_type = IRQ_HT;
286 			sc->htirq_map[irq].ht_source = i;
287 			sc->htirq_map[irq].ht_base = sc->sc_data +
292 			sc->htirq_map[irq].eoi_data =
304 				sc->htirq_map[irq].apple_eoi =
305 				 (sc->htirq_map[irq].ht_base - ptr) + 0x60;
435 cpcht_alloc_msix(device_t dev, device_t child, int *irq)
450 			*irq = MAP_IRQ(cpcht_msipic, i);
462 cpcht_release_msix(device_t dev, device_t child, int irq)
469 	sc->htirq_map[irq & 0xff].irq_type = IRQ_NONE;
476 cpcht_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
496 	*data = irq & 0xff;
507 static void	openpic_cpcht_config(device_t, u_int irq,
509 static void	openpic_cpcht_enable(device_t, u_int irq, u_int vector);
510 static void	openpic_cpcht_unmask(device_t, u_int irq);
511 static void	openpic_cpcht_eoi(device_t, u_int irq);
562 	int err, irq;
584 	for (irq = 0; irq < 4; irq++)
585 		openpic_config(dev, irq, INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
586 	for (irq = 4; irq < 124; irq++)
587 		openpic_config(dev, irq, INTR_TRIGGER_EDGE, INTR_POLARITY_LOW);
601 openpic_cpcht_config(device_t dev, u_int irq, enum intr_trigger trig,
616 	if (cpcht_irqmap != NULL && irq < 128 &&
617 	    cpcht_irqmap[irq].ht_base > 0 && !cpcht_irqmap[irq].edge) {
621 		out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND,
622 		    0x10 + (cpcht_irqmap[irq].ht_source << 1));
625 		ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4);
628 		out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq | HTAPIC_MASK);
633 			cpcht_irqmap[irq].edge = 1;
635 			cpcht_irqmap[irq].edge = 0;
638 		out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq);
645 openpic_cpcht_enable(device_t dev, u_int irq, u_int vec)
650 	openpic_enable(dev, irq, vec);
654 	if (cpcht_irqmap != NULL && irq < 128 &&
655 	    cpcht_irqmap[irq].ht_base > 0) {
659 		out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND,
660 		    0x10 + (cpcht_irqmap[irq].ht_source << 1));
663 		ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4);
665 		out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq);
670 	openpic_cpcht_eoi(dev, irq);
674 openpic_cpcht_unmask(device_t dev, u_int irq)
679 	openpic_unmask(dev, irq);
683 	if (cpcht_irqmap != NULL && irq < 128 &&
684 	    cpcht_irqmap[irq].ht_base > 0) {
688 		out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND,
689 		    0x10 + (cpcht_irqmap[irq].ht_source << 1));
692 		ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4);
694 		out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq);
699 	openpic_cpcht_eoi(dev, irq);
703 openpic_cpcht_eoi(device_t dev, u_int irq)
708 	if (irq == 255)
713 	if (cpcht_irqmap != NULL && irq < 128 &&
714 	    cpcht_irqmap[irq].ht_base > 0 && !cpcht_irqmap[irq].edge) {
717 		if (cpcht_irqmap[irq].apple_eoi) {
718 			off = (cpcht_irqmap[irq].ht_source >> 3) & ~3;
719 			mask = 1 << (cpcht_irqmap[irq].ht_source & 0x1f);
720 			out32rb(cpcht_irqmap[irq].apple_eoi + off, mask);
724 			out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND,
725 			    0x11 + (cpcht_irqmap[irq].ht_source << 1));
726 			out32rb(cpcht_irqmap[irq].ht_base + 4,
727 			    cpcht_irqmap[irq].eoi_data);
733 	openpic_eoi(dev, irq);