Lines Matching refs:caps
205 for (i = 0; i < dev->caps.num_ports - 1; i++) {
207 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
215 for (i = 0; i < dev->caps.num_ports; i++) {
216 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
229 for (i = 1; i <= dev->caps.num_ports; ++i)
230 dev->caps.port_mask[i] = dev->caps.port_type[i];
278 dev->caps.num_ports = dev_cap->num_ports;
279 for (i = 1; i <= dev->caps.num_ports; ++i) {
280 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
281 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
282 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
283 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
284 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
285 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
286 dev->caps.def_mac[i] = dev_cap->def_mac[i];
287 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
288 dev->caps.trans_type[i] = dev_cap->trans_type[i];
289 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
290 dev->caps.wavelength[i] = dev_cap->wavelength[i];
291 dev->caps.trans_code[i] = dev_cap->trans_code[i];
294 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
295 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
296 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
297 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
298 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
299 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
300 dev->caps.max_wqes = dev_cap->max_qp_sz;
301 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
302 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
303 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
304 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
305 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
306 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
307 dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM;
313 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
314 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
315 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
316 dev->caps.mtts_per_seg = 1 << log_mtts_per_seg;
317 dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
318 dev->caps.mtts_per_seg);
319 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
320 dev->caps.reserved_uars = dev_cap->reserved_uars;
321 dev->caps.reserved_pds = dev_cap->reserved_pds;
322 dev->caps.mtt_entry_sz = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz;
323 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
324 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
325 dev->caps.flags = dev_cap->flags;
326 dev->caps.bmme_flags = dev_cap->bmme_flags;
327 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
328 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
329 dev->caps.udp_rss = dev_cap->udp_rss;
330 dev->caps.loopback_support = dev_cap->loopback_support;
331 dev->caps.wol = dev_cap->wol;
332 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
333 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
335 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
338 dev->caps.log_num_macs = log_num_mac;
339 dev->caps.log_num_prios = use_prio ? 3 : 0;
341 for (i = 1; i <= dev->caps.num_ports; ++i) {
342 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
343 if (dev->caps.supported_type[i]) {
344 if (dev->caps.supported_type[i] != MLX4_PORT_TYPE_ETH)
345 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
347 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
349 dev->caps.possible_type[i] = dev->caps.port_type[i];
351 dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO;
353 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
354 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
357 i, 1 << dev->caps.log_num_macs);
359 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
362 dev->caps.counters_mode = get_counters_mode(dev_cap->flags);
363 dev->caps.max_basic_counters = 1 << ilog2(dev_cap->max_basic_counters);
364 dev->caps.max_ext_counters = 1 << ilog2(dev_cap->max_ext_counters);
366 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
367 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
368 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
369 (1 << dev->caps.log_num_macs) *
370 (1 << dev->caps.log_num_vlans) *
371 (1 << dev->caps.log_num_prios) *
372 dev->caps.num_ports;
374 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
375 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
376 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR];
388 for (i = 1; i <= dev->caps.num_ports; i++)
389 config->port_type[i] = dev->caps.possible_type[i];
399 for (i = 1; i <= dev->caps.num_ports; i++)
400 config->port_type[i] = dev->caps.possible_type[i];
418 for (port = 0; port < dev->caps.num_ports; port++) {
421 if (port_types[port] != dev->caps.port_type[port + 1]) {
423 dev->caps.port_type[port + 1] = port_types[port];
428 for (port = 1; port <= dev->caps.num_ports; port++) {
456 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
458 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
493 mdev->caps.possible_type[info->port] = info->tmp_type;
495 for (i = 0; i < mdev->caps.num_ports; i++) {
497 mdev->caps.possible_type[i+1];
499 types[i] = mdev->caps.port_type[i+1];
503 if (++priv->changed_ports < mdev->caps.num_ports)
509 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
510 for (i = 1; i <= mdev->caps.num_ports; i++) {
511 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
512 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
533 for (i = 0; i < mdev->caps.num_ports; i++)
605 cmpt_entry_sz, dev->caps.num_qps,
606 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
615 cmpt_entry_sz, dev->caps.num_srqs,
616 dev->caps.reserved_srqs, 0, 0);
624 cmpt_entry_sz, dev->caps.num_cqs,
625 dev->caps.reserved_cqs, 0, 0);
634 dev->caps.num_eqs, dev->caps.num_eqs, 0, 0);
691 dev->caps.num_eqs, dev->caps.num_eqs,
702 * dev->caps.mtt_entry_sz below is really the MTT segment
705 dev->caps.reserved_mtts =
706 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
707 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
711 dev->caps.mtt_entry_sz,
712 dev->caps.num_mtt_segs,
713 dev->caps.reserved_mtts, 1, 0);
722 dev->caps.num_mpts,
723 dev->caps.reserved_mrws, 1, 1);
732 dev->caps.num_qps,
733 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
743 dev->caps.num_qps,
744 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
754 dev->caps.num_qps,
755 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
765 dev->caps.num_qps,
766 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
776 dev->caps.num_cqs,
777 dev->caps.reserved_cqs, 0, 0);
786 dev->caps.num_srqs,
787 dev->caps.reserved_srqs, 0, 0);
800 dev->caps.num_mgms + dev->caps.num_amgms,
801 dev->caps.num_mgms + dev->caps.num_amgms,
882 bf_start = pci_resource_start(dev->pdev, 2) + (dev->caps.num_uars << PAGE_SHIFT);
883 bf_len = pci_resource_len(dev->pdev, 2) - (dev->caps.num_uars << PAGE_SHIFT);
951 for (i = 1; i <= dev->caps.num_ports; i++) {
952 dev->caps.possible_type[i] = config->port_type[i];
954 dev->caps.port_type[i] = config->port_type[i];
969 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1012 switch (dev->caps.counters_mode) {
1014 nent = dev->caps.max_basic_counters;
1017 nent = dev->caps.max_ext_counters;
1031 switch (dev->caps.counters_mode) {
1045 switch (dev->caps.counters_mode) {
1060 switch (dev->caps.counters_mode) {
1140 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1145 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
1188 for (port = 1; port <= dev->caps.num_ports; port++) {
1194 "caps = 0\n", port, err);
1195 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1256 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1280 dev->caps.num_comp_vectors = nreq - 1;
1291 dev->caps.num_comp_vectors = 1;
1464 for (port = 1; port <= dev->caps.num_ports; port++) {
1559 for (p = 1; p <= dev->caps.num_ports; p++) {