mips/mips/support.S

147 	move		t0, a2
161 	PTR_SUBU	a2, t0, a2		# if the 4th arg was non-NULL
542 	move	t0, a2
546 	sc	t0, 0(a0)		# store word
547 	beqz	t0, 1b
569 	move	t0, a2
573 	scd	t0, 0(a0)		# store double word
574 	beqz	t0, 1b
689 	PTR_ADDU	t0, a0, a2		# t0 = end of s1 region
690 	sltu	t1, a1, t0
699 	lb	v1, -1(t0)		# copy bytes backwards,
700 	PTR_SUBU	t0, t0, 1		#   doesnt happen often so do slow way
702 	bne	t0, a0, 1b
783 	PTR_SUBU	t0, zero, a0		# compute # bytes to word align address
784 	and	t0, t0, 3
785 	beq	t0, zero, 1f		# skip if word aligned
786 	PTR_SUBU	a2, a2, t0		# subtract from remaining count
788 	PTR_ADDU	a0, a0, t0
791 	PTR_SUBU	t0, a2, v1
792 	PTR_SUBU	a2, a2, t0
793 	PTR_ADDU	t0, t0, a0		# compute ending address
802 	bne	a0, t0, 2b		#  unrolling loop does not help
807 	PTR_ADDU	t0, a2, a0		# compute ending address
816 	bne	a0, t0, 1b
964 	move	t0, zero
965 	sc	t0, 0(a0)
966 	beq	t0, zero, 1b
984 	ll	t0, 0(a0)
986 	bne	t0, a1, 2f
1008 	ll	t0, 0(a0)
1010 	move	v0, t0
1028 	ll	t0, 0(a0)
1029 	or	t0, t0, a1
1030 	sc	t0, 0(a0)
1031 	beq	t0, zero, 1b
1049 	ll	t0, 0(a0)
1050 	addu	t0, t0, a1
1051 	sc	t0, 0(a0)
1052 	beq	t0, zero, 1b
1071 	ll	t0, 0(a0)
1072 	and	t0, t0, a1	# t1 has the new lower 16 bits
1073 	sc	t0, 0(a0)
1074 	beq	t0, zero, 1b
1092 	ll	t0, 0(a0)
1093 	subu	t0, t0, a1
1094 	sc	t0, 0(a0)
1095 	beq	t0, zero, 1b
1116 	ll	t0, 0(a0)
1117 	or	t0, t0, a1
1118 	sc	t0, 0(a0)
1119 	beq	t0, zero, 1b
1138 	ll	t0, 0(a0)
1139 	move	t1, t0
1142 	srl	t0, t0, 16	# preserve original top 16 bits
1143 	sll	t0, t0, 16
1144 	or	t0, t0, t1
1145 	sc	t0, 0(a0)
1146 	beq	t0, zero, 1b
1165 	ll	t0, 0(a0)
1166 	move	t1, t0
1170 	srl	t0, t0, 16	# preserve original top 16 bits
1171 	sll	t0, t0, 16
1172 	or	t0, t0, t1
1173 	sc	t0, 0(a0)
1174 	beq	t0, zero, 1b
1192 	ll	t0, 0(a0)
1193 	move	t1, t0
1197 	srl	t0, t0, 16	# preserve original top 16 bits
1198 	sll	t0, t0, 16
1199 	or	t0, t0, t1
1200 	sc	t0, 0(a0)
1201 	beq	t0, zero, 1b
1219 	ll	t0, 0(a0)
1220 	move	t1, t0
1224 	srl	t0, t0, 8	# preserve original top 24 bits
1225 	sll	t0, t0, 8
1226 	or	t0, t0, t1
1227 	sc	t0, 0(a0)
1228 	beq	t0, zero, 1b
1247 	ll	t0, 0(a0)
1248 	move	t1, t0
1252 	srl	t0, t0, 8	# preserve original top 24 bits
1253 	sll	t0, t0, 8
1254 	or	t0, t0, t1
1255 	sc	t0, 0(a0)
1256 	beq	t0, zero, 1b
1283 	ld	t0, (a1)
1286 	sd	t0, (a0)
1306 	ld	t0, (a0)
1309 	sd	t0, (a1)
1419 	GET_CPU_PCPU(t0)
1420 	lw	t0, PC_CURTHREAD(t0)
1421 	lw	t0, TD_PCB(t0)
1430 	PTR_LI	t0, VM_MAXUSER_ADDRESS /* verify address validity */
1431 	blt	a0, t0, fusufault		/* trap faults */
1443 	move	t0, a2			/* setup value to write */
1444 	sc	t0, 0(a0)		/* write if address still locked */
1445 	beq	t0, zero, 1b			/* if it failed, spin */
1508 	mfc0	t0, MIPS_COP_0_STATUS		# turn off interrupts
1509 	and	t1, t0, ~(MIPS_SR_INT_IE)
1527 	mtc0	t0, MIPS_COP_0_STATUS		# restore intr status.
1544 	mfc0	t0, MIPS_COP_0_STATUS		# turn off interrupts
1545 	and	t1, t0, ~(MIPS_SR_INT_IE)
1566 	mtc0	t0, MIPS_COP_0_STATUS		# restore intr status.