Lines Matching defs:val64
61 u64 val64;
96 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(action) |
104 (u32) bVAL32(val64, 32),
111 (u32) bVAL32(val64, 0),
128 val64 = vxge_os_pio_mem_read64(pdev, regh0,
131 if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
711 u64 val64 = 0ULL;
734 val64 |= mBIT(i);
740 return (val64);
824 u64 val64;
859 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
868 (u32) bVAL32(val64, 32),
874 (u32) bVAL32(val64, 0),
891 val64 = vxge_os_pio_mem_read64(pdev, regh0,
894 if (!(val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)) {
929 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
937 (u32) bVAL32(val64, 32),
943 (u32) bVAL32(val64, 0), &vpath_reg->rts_access_steer_ctrl);
957 val64 = vxge_os_pio_mem_read64(pdev, regh0,
959 if (!(val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)) {
965 val64 = vxge_os_pio_mem_read64(pdev, regh0,
967 switch (VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_RET_CODE(val64)) {
976 i += (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_UPGRADE_GET_SKIP_BYTES(val64);
998 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
1008 (u32) bVAL32(val64, 32),
1015 (u32) bVAL32(val64, 0),
1032 val64 = vxge_os_pio_mem_read64(pdev, regh0,
1035 if (!(val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)) {
1061 u64 val64;
1095 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
1104 (u32) bVAL32(val64, 32),
1111 (u32) bVAL32(val64, 0),
1149 u64 val64;
1183 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
1192 (u32) bVAL32(val64, 32),
1199 (u32) bVAL32(val64, 0),
1235 u64 val64;
1269 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
1278 (u32) bVAL32(val64, 32),
1285 (u32) bVAL32(val64, 0),
1303 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
1307 if (!(val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)) {
1332 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(
1341 (u32) bVAL32(val64, 32),
1348 (u32) bVAL32(val64, 0),
1366 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
1370 if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
1469 u64 val64;
1490 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(action) |
1504 val64 |= VXGE_HAL_RTS_ACCESS_STEER_CTRL_TABLE_SEL;
1509 (u32) bVAL32(val64, 32),
1516 (u32) bVAL32(val64, 0),
1535 val64 = vxge_os_pio_mem_read64(
1540 if (!(val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)) {
1618 u64 val64;
1655 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(action) |
1662 (u32) bVAL32(val64, 32),
1669 (u32) bVAL32(val64, 0),
1688 val64 = vxge_os_pio_mem_read64(
1693 if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
1823 u64 val64;
1845 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(action) |
1853 (u32) bVAL32(val64, 32),
1860 (u32) bVAL32(val64, 0),
1877 val64 = vxge_os_pio_mem_read64(pdev, regh0,
1880 if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
2491 u64 val64;
2508 val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(port);
2511 val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_SRC_DEST_SEL;
2514 val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_TCP_UDP_SEL;
2520 val64,
2549 u64 val64;
2572 &val64,
2576 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(val64);
2578 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(val64);
2579 *port = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(val64);
2606 u64 val64;
2629 &val64,
2633 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(val64);
2636 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(val64);
2638 *port = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(val64);
2667 u64 val64;
2684 val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(port);
2687 val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_SRC_DEST_SEL;
2690 val64 = VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_TCP_UDP_SEL;
2696 val64,
2830 u64 val64;
2854 &val64,
2858 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ALG_SEL(val64);
2861 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV4_EN(val64))
2865 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV4_EN(val64))
2869 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EN(val64))
2873 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EN(val64))
2878 val64)) ? 1 : 0;
2881 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EX_EN(val64))
2885 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(val64))
2889 VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_BUCKET_SIZE(val64);
3061 u64 val64;
3082 &val64,
3093 val64);
3097 val64);
3133 u64 val64;
3163 val64 =
3181 val64,
3221 u64 val64;
3255 &val64,
3263 val64);
3267 val64);
3271 val64);
3275 val64);
3278 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK(val64);
3281 VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK(val64);
3688 u64 val64;
3718 val64 = vxge_os_pio_mem_read64(
3723 val64 |= VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN |
3731 val64,
3752 u64 val64;
3781 val64 = vxge_os_pio_mem_read64(
3788 val64 &= ~VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
3793 val64 &= ~VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
3798 val64 &= ~VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
3803 val64 &= ~VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
3809 val64,
3829 u64 val64;
3861 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3865 val64 |= VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
3869 val64,
3889 u64 val64;
3919 val64 = vxge_os_pio_mem_read64(
3924 val64 &= ~VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
3929 val64,
3951 u64 val64;
3980 val64 = vxge_os_pio_mem_read64(
3985 val64 |= VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
3990 val64,
4015 u64 val64;
4045 val64 = vxge_os_pio_mem_read64(
4050 val64 &= ~VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
4055 val64,
4078 u64 val64;
4107 val64 = vxge_os_pio_mem_read64(
4112 val64 |= VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
4117 val64,
4141 u64 val64;
4171 val64 = vxge_os_pio_mem_read64(
4176 val64 &= ~VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
4181 val64,
4204 u64 val64;
4233 val64 = vxge_os_pio_mem_read64(
4238 val64 |= VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
4243 val64,
4265 u64 val64;
4295 val64 = vxge_os_pio_mem_read64(
4300 val64 &= ~VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
4305 val64,
4327 u64 val64;
4356 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4360 val64 |= VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4364 val64,
4387 u64 val64;
4416 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4420 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4424 val64,
4449 u64 val64;
4472 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4478 val64 |= VXGE_HAL_TPA_CFG_IGNORE_FRAME_ERR;
4480 val64 &= ~VXGE_HAL_TPA_CFG_IGNORE_FRAME_ERR;
4485 val64 &= ~VXGE_HAL_TPA_CFG_IPV6_STOP_SEARCHING;
4487 val64 |= VXGE_HAL_TPA_CFG_IPV6_STOP_SEARCHING;
4492 val64 |= VXGE_HAL_TPA_CFG_L4_PSHDR_PRESENT;
4494 val64 &= ~VXGE_HAL_TPA_CFG_L4_PSHDR_PRESENT;
4499 val64 |= VXGE_HAL_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS;
4501 val64 &= ~VXGE_HAL_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS;
4506 val64,
4516 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4522 val64 |= VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN;
4524 val64 &= ~VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN;
4529 val64 |=
4532 val64 &=
4538 val64,
4564 u64 val64;
4587 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4593 val64 |= VXGE_HAL_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH;
4595 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH;
4600 val64 |= VXGE_HAL_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH;
4602 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH;
4607 val64 |= VXGE_HAL_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH;
4609 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH;
4614 val64 |= VXGE_HAL_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH;
4616 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH;
4621 val64 |= VXGE_HAL_XMAC_RPA_VCFG_L4_INCL_CF;
4623 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_L4_INCL_CF;
4628 val64 |= VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4630 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4635 val64,
4645 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4651 val64 |= VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
4653 val64 &= ~VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
4658 val64 |= VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
4660 val64 &= ~VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
4665 val64 |= VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
4667 val64 &= ~VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
4672 val64 |= VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
4674 val64 &= ~VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
4679 val64,
4687 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4693 val64 |= VXGE_HAL_FAU_RPA_VCFG_L4_COMP_CSUM;
4695 val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L4_COMP_CSUM;
4700 val64 |= VXGE_HAL_FAU_RPA_VCFG_L3_INCL_CF;
4702 val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L3_INCL_CF;
4707 val64 |= VXGE_HAL_FAU_RPA_VCFG_L3_COMP_CSUM;
4709 val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L3_COMP_CSUM;
4714 val64,
4741 u64 val64;
4909 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4913 /* val64 |= VXGE_HAL_TIM_SET_INT_EN_VP(1 << (16 - vpath->vp_id)); */
4917 (u32) bVAL32(val64, 0),
4988 u64 val64;
5014 val64 = VXGE_HAL_TIM_CLR_INT_EN_VP(1 << (16 - vpath->vp_id));
5018 (u32) bVAL32(val64, 0),
5135 u64 val64;
5151 val64 = VXGE_HAL_VPATH_GENERAL_INT_MASK_PIC_INT |
5159 (u32) bVAL32(val64, 0),
5164 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5168 val64 |= vBIT(0xf, (vp->vpath->vp_id * 4), 4);
5172 val64,
5199 u64 val64;
5227 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5231 val64 &= ~(vBIT(0xf, (vp->vpath->vp_id * 4), 4));
5235 val64,
5300 u64 val64;
5319 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5323 if (val64 & VXGE_HAL_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK) {
5327 if (val64 &
5358 u64 val64;
5377 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5381 if (val64 &
5410 u64 val64;
5454 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5460 (ptr_t) val64);
5461 if (val64 & VXGE_HAL_GENERAL_ERRORS_REG_INI_SERR_DET) {
5486 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5492 (ptr_t) val64);
5494 if (val64 &
5502 if (val64 & VXGE_HAL_PCI_CONFIG_ERRORS_REG_UNCOR_ERR) {
5509 if (val64 & VXGE_HAL_PCI_CONFIG_ERRORS_REG_COR_ERR) {
5525 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5531 (ptr_t) val64);
5533 if (val64 &
5563 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5569 (ptr_t) val64);
5604 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5609 "prc_alarm_reg = 0x"VXGE_OS_STXFMT, (ptr_t) val64);
5611 if (val64 & VXGE_HAL_PRC_ALARM_REG_PRC_RING_BUMP) {
5618 if (val64 & VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ERR) {
5642 if (val64 & VXGE_HAL_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT) {
5665 if (val64 & VXGE_HAL_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR) {
5684 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5690 (ptr_t) val64);
5692 if (val64 &
5718 if (val64 & VXGE_HAL_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW) {
5726 if (val64 &
5734 if (val64 &
5742 if (val64 &
5750 if (val64 & VXGE_HAL_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS) {
5766 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5772 (ptr_t) val64);
5774 if (val64 &
5796 if (val64 &
5805 if (val64 &
5813 if (val64 &
5835 if (val64 &
5844 if (val64 &
5852 if (val64 &
5875 if (val64 &
5883 if (val64 &
5913 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5919 (ptr_t) val64);
5921 if (val64 &
5924 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5928 __hal_ifmsg_wmsg_process(vpath, val64);
5966 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5972 (ptr_t) val64);
5974 if (((val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT) &&
5975 (!(val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK))) ||
5976 ((val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT_OCCURRED) &&
5977 (!(val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK_OCCURRED)))) {
5990 if (((val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK) &&
5991 (!(val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT))) ||
5992 ((val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_OK_OCCURRED) &&
5993 (!(val64 & VXGE_HAL_ASIC_NTWK_VP_ERR_REG_SUS_FAULT_OCCURRED)))) {
6066 u64 val64;
6092 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6096 if (vxge_os_unlikely(!val64)) {
6104 if (vxge_os_unlikely(val64 == VXGE_HAL_ALL_FOXES)) {
6121 if (val64 &
6127 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6131 *reason = bVAL4(val64, (vpath->vp_id * 4));
6134 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6138 *reason = bVAL4(val64, 0);
6146 if (vxge_os_unlikely(val64 &
6155 if (vxge_os_unlikely(val64 &
6164 if (vxge_os_unlikely(val64 &
6338 u64 val64;
6370 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6374 val64 |= vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
6378 val64,
6383 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6387 val64 |= VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(VXGE_HAL_INTR_TX);
6391 (u32) bVAL32(val64, 0),
6473 u64 val64;
6505 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6509 val64 &= ~vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
6513 val64,
6518 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6522 val64 &=
6527 (u32) bVAL32(val64, 0),
6548 u64 val64;
6578 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6582 val64 |= vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
6586 val64,
6591 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6595 val64 |= VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(VXGE_HAL_INTR_RX);
6599 (u32) bVAL32(val64, 0),
6681 u64 val64;
6711 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6715 val64 &= ~vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
6719 val64,
6724 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6728 val64 &=
6733 (u32) bVAL32(val64, 0),
6754 u64 val64;
6778 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6782 val64 |= vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4) |
6787 val64,
6792 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6796 val64 |=
6802 (u32) bVAL32(val64, 0),
6825 u64 val64;
6847 val64 = 0;
6852 val64 |= vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
6854 val64 &= ~vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
6857 val64 |= vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
6859 val64 &= ~vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
6863 val64,
6869 val64 |= vBIT(VXGE_HAL_INTR_TX, 0, 4);
6872 val64 |= vBIT(VXGE_HAL_INTR_RX, 0, 4);
6874 val64 &= ~vBIT(VXGE_HAL_INTR_RX, 0, 4);
6878 (u32) bVAL32(val64, 0),
6898 u64 val64;
6922 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6927 val64 &= ~vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
6929 val64 |= vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
6932 val64 &= ~vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
6934 val64 |= vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
6938 val64,
6943 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6948 val64 &= ~VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(
6951 val64 |= VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(
6955 val64 &= ~VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(
6958 val64 |= VXGE_HAL_TIM_INT_MASK1_TIM_INT_MASK1(
6963 (u32) bVAL32(val64, 0),
7057 u64 val64;
7097 val64 = VXGE_HAL_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(
7112 val64,
7273 u64 val64;
7283 val64 = VXGE_HAL_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(tim_msix_id[0]) |
7289 val64 |= VXGE_HAL_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(
7295 val64,
7674 u64 val64;
7690 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
7695 (u32) VXGE_HAL_VPATH_IS_FIRST_GET_VPATH_IS_FIRST(val64);
7697 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
7702 (u32) VXGE_HAL_TIM_VPATH_ASSIGNMENT_GET_BMAP_ROOT(val64);
7708 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
7714 val64)) {
7717 val64);
7723 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
7728 (u32) VXGE_HAL_XMAC_VSPORT_CHOICES_VP_GET_VSPORT_VECTOR(val64);
7732 if (val64 & mBIT(i))
7737 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
7741 if (val64 & VXGE_HAL_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK) {
7752 if (val64 &
7820 u64 val64;
7835 val64 = VXGE_HAL_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id));
7838 (u32) bVAL32(val64, 0),
7916 u64 val64;
7933 val64 = VXGE_HAL_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(
7938 (u32) bVAL32(val64, 0),
7969 u64 val64;
7993 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
7999 val64 &= ~VXGE_HAL_PRC_CFG1_RX_TIMER_VAL(0x1fffffff);
8000 val64 |= VXGE_HAL_PRC_CFG1_RX_TIMER_VAL(
8004 val64 |= VXGE_HAL_PRC_CFG1_RTI_TINT_DISABLE;
8009 val64 |= VXGE_HAL_PRC_CFG1_GREEDY_RETURN;
8011 val64 &= ~VXGE_HAL_PRC_CFG1_GREEDY_RETURN;
8017 val64 |= VXGE_HAL_PRC_CFG1_RX_TIMER_CI;
8019 val64 &= ~VXGE_HAL_PRC_CFG1_RX_TIMER_CI;
8024 val64,
8027 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8034 val64 &= ~VXGE_HAL_PRC_CFG7_SCATTER_MODE(0x3);
8038 val64 |= VXGE_HAL_PRC_CFG7_SCATTER_MODE(
8042 val64 |= VXGE_HAL_PRC_CFG7_SCATTER_MODE(
8046 val64 |= VXGE_HAL_PRC_CFG7_SCATTER_MODE(
8054 val64,
8057 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8066 val64 |= VXGE_HAL_PRC_CFG6_DOORBELL_MODE_EN;
8068 val64 &= ~VXGE_HAL_PRC_CFG6_DOORBELL_MODE_EN;
8073 ((val64 & VXGE_HAL_PRC_CFG6_DOORBELL_MODE_EN) ?
8081 val64,
8090 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8094 val64 |= VXGE_HAL_PRC_CFG4_IN_SVC;
8096 val64 &= ~VXGE_HAL_PRC_CFG4_RING_MODE(0x3);
8099 val64 |= VXGE_HAL_PRC_CFG4_RING_MODE(
8104 val64 |= VXGE_HAL_PRC_CFG4_RING_MODE(
8107 val64 |= VXGE_HAL_PRC_CFG4_RING_MODE(
8115 val64 &= ~(VXGE_HAL_PRC_CFG4_FRM_NO_SNOOP |
8120 val64 |= VXGE_HAL_PRC_CFG4_RXD_NO_SNOOP;
8124 val64 |= VXGE_HAL_PRC_CFG4_FRM_NO_SNOOP;
8128 val64 |= VXGE_HAL_PRC_CFG4_FRM_NO_SNOOP;
8129 val64 |= VXGE_HAL_PRC_CFG4_RXD_NO_SNOOP;
8137 val64 |= VXGE_HAL_PRC_CFG4_RTH_DISABLE;
8139 val64 &= ~VXGE_HAL_PRC_CFG4_RTH_DISABLE;
8141 val64 |= VXGE_HAL_PRC_CFG4_SIGNAL_BENIGN_OVFLW;
8143 val64 |= VXGE_HAL_PRC_CFG4_BIMODAL_INTERRUPT;
8148 val64 &= ~VXGE_HAL_PRC_CFG4_BACKOFF_INTERVAL(0xffffff);
8150 val64 |= VXGE_HAL_PRC_CFG4_BACKOFF_INTERVAL(
8157 val64,
8178 u64 val64;
8210 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8215 (u32) VXGE_HAL_RXDMEM_SIZE_PRC_RXDMEM_SIZE(val64) * 8;
8226 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8231 (u32) VXGE_HAL_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(val64 + 1) / 2;
8254 val64 = 0;
8257 val64 |= VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(
8261 val64 |= VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_1(
8266 val64,
8274 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8280 val64 &= ~(VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) |
8283 val64 |= VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE(
8293 val64 |=
8296 val64 &=
8303 val64,
8306 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8312 val64 &= ~(VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE(0x3) |
8315 val64 |= VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE(
8325 val64 |=
8328 val64 &=
8335 val64,
8396 u64 val64;
8421 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8428 val64 |=
8431 val64 &=
8438 val64 |=
8441 val64 &=
8448 val64 |=
8451 val64 &=
8458 val64 |=
8461 val64 &=
8468 val64 |= VXGE_HAL_XMAC_RPA_VCFG_L4_INCL_CF;
8470 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_L4_INCL_CF;
8476 val64 |= VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
8478 val64 &= ~VXGE_HAL_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
8483 val64,
8486 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8492 val64 &= ~VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
8495 val64 |= VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
8499 val64 |= VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
8506 val64 |= VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN;
8508 val64 &=
8511 if (val64 & VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN) {
8523 val64 |= VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
8525 val64 &=
8528 if (val64 & VXGE_HAL_RXMAC_VCFG0_MCAST_ALL_ADDR_EN) {
8540 val64 |= VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
8542 val64 &= ~VXGE_HAL_RXMAC_VCFG0_BCAST_EN;
8544 if (val64 & VXGE_HAL_RXMAC_VCFG0_BCAST_EN) {
8556 val64 |= VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
8558 val64 &= ~VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN;
8560 if (val64 & VXGE_HAL_RXMAC_VCFG0_ALL_VID_EN) {
8570 val64 |= VXGE_HAL_RXMAC_VCFG0_UCAST_ALL_ADDR_EN |
8578 val64,
8581 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8585 val64 &= ~(VXGE_HAL_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) |
8590 val64 |=
8598 val64 |= VXGE_HAL_RXMAC_VCFG1_CONTRIB_L2_FLOW;
8600 val64 &= ~VXGE_HAL_RXMAC_VCFG1_CONTRIB_L2_FLOW;
8605 val64,
8608 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8615 val64 |= VXGE_HAL_FAU_RPA_VCFG_L4_COMP_CSUM;
8617 val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L4_COMP_CSUM;
8623 val64 |= VXGE_HAL_FAU_RPA_VCFG_L3_INCL_CF;
8625 val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L3_INCL_CF;
8631 val64 |= VXGE_HAL_FAU_RPA_VCFG_L3_COMP_CSUM;
8633 val64 &= ~VXGE_HAL_FAU_RPA_VCFG_L3_COMP_CSUM;
8638 val64,
8644 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8651 val64 |= VXGE_HAL_TPA_CFG_IGNORE_FRAME_ERR;
8653 val64 &= ~VXGE_HAL_TPA_CFG_IGNORE_FRAME_ERR;
8659 val64 |= VXGE_HAL_TPA_CFG_IPV6_STOP_SEARCHING;
8661 val64 &= ~VXGE_HAL_TPA_CFG_IPV6_STOP_SEARCHING;
8667 val64 |= VXGE_HAL_TPA_CFG_L4_PSHDR_PRESENT;
8669 val64 &= ~VXGE_HAL_TPA_CFG_L4_PSHDR_PRESENT;
8675 val64 |=
8678 val64 &=
8684 val64,
8687 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8694 val64 |=
8697 val64 &=
8704 val64 |= VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING;
8706 val64 &= ~VXGE_HAL_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING;
8711 val64,
8734 u64 val64;
8769 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8773 val64 |= VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN;
8776 val64 = 0x1000150012000100ULL; /* override for HPISS */
8780 val64,
8783 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8787 val64 |= VXGE_HAL_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(0x5BE9) |
8794 val64,
8806 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8810 val64 |= VXGE_HAL_TIM_PCI_CFG_ADD_PAD;
8815 val64 |= VXGE_HAL_TIM_PCI_CFG_NO_SNOOP;
8817 val64 &= ~VXGE_HAL_TIM_PCI_CFG_NO_SNOOP;
8822 val64,
8827 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8833 val64 &=
8835 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(
8839 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_BITMP_EN;
8844 val64 |=
8847 val64 &=
8854 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TXD_CNT_EN;
8856 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TXD_CNT_EN;
8862 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_AC;
8864 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_AC;
8870 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
8872 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
8877 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_A(0x3f);
8878 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_A(
8884 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_B(0x3f);
8885 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_B(
8891 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_C(0x3f);
8892 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_C(
8898 val64,
8901 vpath->tim_tti_cfg1_saved = val64;
8903 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8909 val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_A(0xffff);
8910 val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_A(
8916 val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_B(0xffff);
8917 val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_B(
8923 val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_C(0xffff);
8924 val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_C(
8930 val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_D(0xffff);
8931 val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_D(
8937 val64,
8940 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8947 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_TIMER_RI;
8949 val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_TIMER_RI;
8954 val64 &=
8956 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(
8962 val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(
8964 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(
8970 val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
8971 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_UTIL_SEL(
8977 val64 &=
8979 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_LTIMER_VAL(
8985 val64,
8988 vpath->tim_tti_cfg3_saved = val64;
8993 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
8999 val64 &=
9001 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(
9005 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_BITMP_EN;
9010 val64 |=
9013 val64 &=
9020 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TXD_CNT_EN;
9022 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TXD_CNT_EN;
9028 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_AC;
9030 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_AC;
9036 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
9038 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
9043 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_A(0x3f);
9044 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_A(
9050 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_B(0x3f);
9051 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_B(
9057 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_URNG_C(0x3f);
9058 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_URNG_C(
9064 val64,
9067 vpath->tim_rti_cfg1_saved = val64;
9069 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
9075 val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_A(0xffff);
9076 val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_A(
9082 val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_B(0xffff);
9083 val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_B(
9089 val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_C(0xffff);
9090 val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_C(
9096 val64 &= ~VXGE_HAL_TIM_CFG2_INT_NUM_UEC_D(0xffff);
9097 val64 |= VXGE_HAL_TIM_CFG2_INT_NUM_UEC_D(
9103 val64,
9106 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
9113 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_TIMER_RI;
9115 val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_TIMER_RI;
9120 val64 &=
9122 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(
9128 val64 &=
9130 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(
9136 val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
9137 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_UTIL_SEL(
9143 val64 &=
9145 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_LTIMER_VAL(
9151 val64,
9154 vpath->tim_rti_cfg3_saved = val64;
9157 val64 = 0;
9162 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(1) |
9169 val64,
9212 u64 val64;
9233 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
9237 new_qw_count = (u32) VXGE_HAL_PRC_RXD_DOORBELL_GET_NEW_QW_CNT(val64);
9239 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
9243 rxd_spat = (u32) VXGE_HAL_PRC_CFG6_GET_RXD_SPAT(val64);
9314 u64 val64;
9342 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
9346 val64 &= ~VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
9347 val64 |= VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu);
9351 val64,
9376 u64 val64;
9392 val64 = 0;
9395 val64 = 1;
9398 val64 = 2;
9401 val64 = 3;
9405 val64 = 4;
9408 val64 = 5;
9411 val64 = 6;
9416 val64,
9437 u64 val64;
9510 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
9514 val64 |= VXGE_HAL_QCC_PCI_CFG_ADD_PAD_CQE_SPACE |
9524 val64 |= VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_CQE_SPACE |
9528 val64 &= ~(VXGE_HAL_QCC_PCI_CFG_NO_SNOOP_CQE_SPACE |
9535 val64,
9538 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
9545 val64 |= VXGE_HAL_H2L_VPATH_CONFIG_OD_NO_SNOOP;
9547 val64 &= ~VXGE_HAL_H2L_VPATH_CONFIG_OD_NO_SNOOP;
9552 val64,
9555 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
9562 val64 |= VXGE_HAL_PH2L_VP_CFG0_NOSNOOP_DATA;
9564 val64 &= ~VXGE_HAL_PH2L_VP_CFG0_NOSNOOP_DATA;
9569 val64,
9581 val64 = VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_GEN_INT_AFTER_ABORT |
9587 val64,
10250 u64 val64;
10281 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
10285 val64 |= VXGE_HAL_STATS_CFG0_STATS_ENABLE(
10290 (u32) bVAL32(val64, 0),
10317 u64 val64;
10342 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
10346 val64 &= ~VXGE_HAL_STATS_CFG0_STATS_ENABLE((1 << (16 - vpath->vp_id)));
10350 (u32) bVAL32(val64, 0),
10523 u64 val64;
10545 val64 = VXGE_HAL_XMAC_STATS_ACCESS_CMD_OP(operation) |
10551 (u32) bVAL32(val64, 32),
10557 (u32) bVAL32(val64, 0),
10638 u64 val64;
10663 VXGE_HAL_STATS_GET_VPATH_TX_TTL_ETH_FRMS(val64);
10669 VXGE_HAL_STATS_GET_VPATH_TX_TTL_ETH_OCTETS(val64);
10675 VXGE_HAL_STATS_GET_VPATH_TX_DATA_OCTETS(val64);
10681 VXGE_HAL_STATS_GET_VPATH_TX_MCAST_FRMS(val64);
10687 VXGE_HAL_STATS_GET_VPATH_TX_BCAST_FRMS(val64);
10693 VXGE_HAL_STATS_GET_VPATH_TX_UCAST_FRMS(val64);
10699 VXGE_HAL_STATS_GET_VPATH_TX_TAGGED_FRMS(val64);
10704 VXGE_HAL_STATS_GET_VPATH_TX_VLD_IP(val64);
10710 VXGE_HAL_STATS_GET_VPATH_TX_VLD_IP_OCTETS(val64);
10715 VXGE_HAL_STATS_GET_VPATH_TX_ICMP(val64);
10720 VXGE_HAL_STATS_GET_VPATH_TX_TCP(val64);
10726 VXGE_HAL_STATS_GET_VPATH_TX_RST_TCP(val64);
10732 VXGE_HAL_STATS_GET_VPATH_TX_UDP(val64);
10738 (u32) VXGE_HAL_STATS_GET_VPATH_TX_LOST_IP(val64);
10744 (u32) VXGE_HAL_STATS_GET_VPATH_TX_UNKNOWN_PROTOCOL(val64);
10750 (u32) VXGE_HAL_STATS_GET_VPATH_TX_PARSE_ERROR(val64);
10756 VXGE_HAL_STATS_GET_VPATH_TX_TCP_OFFLOAD(val64);
10762 VXGE_HAL_STATS_GET_VPATH_TX_RETX_TCP_OFFLOAD(val64);
10768 VXGE_HAL_STATS_GET_VPATH_TX_LOST_IP_OFFLOAD(val64);
10787 u64 val64;
10812 VXGE_HAL_STATS_GET_VPATH_RX_TTL_ETH_FRMS(val64);
10817 VXGE_HAL_STATS_GET_VPATH_RX_VLD_FRMS(val64);
10823 VXGE_HAL_STATS_GET_VPATH_RX_OFFLOAD_FRMS(val64);
10829 VXGE_HAL_STATS_GET_VPATH_RX_TTL_ETH_OCTETS(val64);
10835 VXGE_HAL_STATS_GET_VPATH_RX_DATA_OCTETS(val64);
10841 VXGE_HAL_STATS_GET_VPATH_RX_OFFLOAD_OCTETS(val64);
10847 VXGE_HAL_STATS_GET_VPATH_RX_VLD_MCAST_FRMS(val64);
10853 VXGE_HAL_STATS_GET_VPATH_RX_VLD_BCAST_FRMS(val64);
10859 VXGE_HAL_STATS_GET_VPATH_RX_ACC_UCAST_FRMS(val64);
10865 VXGE_HAL_STATS_GET_VPATH_RX_ACC_NUCAST_FRMS(val64);
10871 VXGE_HAL_STATS_GET_VPATH_RX_TAGGED_FRMS(val64);
10877 VXGE_HAL_STATS_GET_VPATH_RX_LONG_FRMS(val64);
10883 VXGE_HAL_STATS_GET_VPATH_RX_USIZED_FRMS(val64);
10889 VXGE_HAL_STATS_GET_VPATH_RX_OSIZED_FRMS(val64);
10895 VXGE_HAL_STATS_GET_VPATH_RX_FRAG_FRMS(val64);
10901 VXGE_HAL_STATS_GET_VPATH_RX_JABBER_FRMS(val64);
10907 VXGE_HAL_STATS_GET_VPATH_RX_TTL_64_FRMS(val64);
10913 VXGE_HAL_STATS_GET_VPATH_RX_TTL_65_127_FRMS(val64);
10919 VXGE_HAL_STATS_GET_VPATH_RX_TTL_128_255_FRMS(val64);
10925 VXGE_HAL_STATS_GET_VPATH_RX_TTL_256_511_FRMS(val64);
10931 VXGE_HAL_STATS_GET_VPATH_RX_TTL_512_1023_FRMS(val64);
10937 VXGE_HAL_STATS_GET_VPATH_RX_TTL_1024_1518_FRMS(val64);
10943 VXGE_HAL_STATS_GET_VPATH_RX_TTL_1519_4095_FRMS(val64);
10949 VXGE_HAL_STATS_GET_VPATH_RX_TTL_4096_8191_FRMS(val64);
10955 VXGE_HAL_STATS_GET_VPATH_RX_TTL_8192_MAX_FRMS(val64);
10961 VXGE_HAL_STATS_GET_VPATH_RX_TTL_GT_MAX_FRMS(val64);
10966 VXGE_HAL_STATS_GET_VPATH_RX_IP(val64);
10971 VXGE_HAL_STATS_GET_VPATH_RX_ACC_IP(val64);
10976 VXGE_HAL_STATS_GET_VPATH_RX_IP_OCTETS(val64);
10981 VXGE_HAL_STATS_GET_VPATH_RX_ERR_IP(val64);
10986 VXGE_HAL_STATS_GET_VPATH_RX_ICMP(val64);
10991 VXGE_HAL_STATS_GET_VPATH_RX_TCP(val64);
10996 VXGE_HAL_STATS_GET_VPATH_RX_UDP(val64);
11001 VXGE_HAL_STATS_GET_VPATH_RX_ERR_TCP(val64);
11007 VXGE_HAL_STATS_GET_VPATH_RX_LOST_FRMS(val64);
11012 VXGE_HAL_STATS_GET_VPATH_RX_LOST_IP(val64);
11018 VXGE_HAL_STATS_GET_VPATH_RX_LOST_IP_OFFLOAD(val64);
11024 (u16) VXGE_HAL_STATS_GET_VPATH_RX_QUEUE_FULL_DISCARD(val64);
11030 (u16) VXGE_HAL_STATS_GET_VPATH_RX_RED_DISCARD(val64);
11036 (u16) VXGE_HAL_STATS_GET_VPATH_RX_SLEEP_DISCARD(val64);
11045 VXGE_HAL_STATS_GET_VPATH_RX_MPA_OK_FRMS(val64);
11134 u64 val64;
11155 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11160 (u32) VXGE_HAL_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64);
11162 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11167 (u32) VXGE_HAL_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64);
11169 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11174 (u32) VXGE_HAL_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64);
11176 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11181 VXGE_HAL_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64);
11183 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11188 VXGE_HAL_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64);
11190 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11195 (u32) VXGE_HAL_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64);
11197 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11202 (u32) VXGE_HAL_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64);
11204 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11210 val64);
11212 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11218 val64);
11220 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11226 val64);
11228 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11234 val64);
11236 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11242 val64);
11244 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11250 val64);
11270 (u32) VXGE_HAL_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64);
11273 (u32) VXGE_HAL_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64);
11279 (u32) VXGE_HAL_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64);
11282 (u32) VXGE_HAL_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64);
11284 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11289 (u16) VXGE_HAL_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64);
11291 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11296 (u32) VXGE_HAL_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64);
11298 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11303 (u16) VXGE_HAL_RXD_RETURNED_GET_RXD_RETURNED(val64);
11306 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11311 (u16) VXGE_HAL_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64);
11313 (u16) VXGE_HAL_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64);
11315 (u16) VXGE_HAL_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64);
11317 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11322 (u16) VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64);
11324 VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64);
11326 (u16) VXGE_HAL_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64);
11328 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11334 val64);
11401 u64 val64;
11422 val64 = VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(action) |
11428 hldev->header.regh0, val64,
11443 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
11447 if (val64 & VXGE_HAL_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)
11589 u64 val64;
11605 val64 = vxge_os_pio_mem_read64(
11610 (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_FUNC_MODE(val64);
11621 u64 val64, data0;
11637 val64 = vxge_os_pio_mem_read64(
11641 *num_funcs = (u32) VXGE_HAL_RTS_ACCESS_STEER_DATA0_GET_NUM_FUNC(val64);
11930 u64 val64, timer;
11938 val64 = vpath->tim_tti_cfg3_saved;
11941 val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
11943 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) |
11948 val64,
11961 u64 val64, timer;
11969 val64 = vpath->tim_rti_cfg3_saved;
11972 val64 &= ~VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
11974 val64 |= VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) |
11979 val64,
11991 u64 val64;
12003 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
12007 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
12008 vpath->tim_rti_cfg1_saved = val64;
12012 val64,
12021 u64 val64;
12033 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
12037 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
12038 vpath->tim_rti_cfg1_saved = val64;
12042 val64,
12051 u64 val64;
12063 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
12067 val64 |= VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
12068 vpath->tim_rti_cfg1_saved = val64;
12072 val64,
12081 u64 val64;
12093 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
12097 val64 &= ~VXGE_HAL_TIM_CFG1_INT_NUM_TIMER_CI;
12098 vpath->tim_rti_cfg1_saved = val64;
12102 val64,