Lines Matching defs:val64
85 u64 val64;
103 val64 = vxge_os_pio_mem_read64(pdev, regh0,
106 toc_reg = (vxge_hal_toc_reg_t *) ((void *)(bar0 + val64));
108 val64 = vxge_os_pio_mem_read64(pdev, regh0,
111 vpath_reg = (vxge_hal_vpath_reg_t *) ((void *)(bar0 + val64));
113 val64 = __hal_vpath_vpath_map_get(pdev, regh0, 0, 0, func, vpath_reg);
118 return (val64);
239 u64 val64, vpath_mask;
263 val64 = vxge_os_pio_mem_read64(pdev, regh0,
266 toc_reg = (vxge_hal_toc_reg_t *) ((void *)(bar0 + val64));
268 val64 =
271 common_reg = (vxge_hal_common_reg_t *) ((void *)(bar0 + val64));
276 val64 = vxge_os_pio_mem_read64(pdev, regh0,
280 VXGE_HAL_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
287 val64 = vxge_os_pio_mem_read64(pdev, regh0,
290 vpmgmt_reg = (vxge_hal_vpmgmt_reg_t *) ((void *)(bar0 + val64));
292 val64 = vxge_os_pio_mem_read64(pdev, regh0,
295 func_id = (u32) VXGE_HAL_VPATH_TO_FUNC_MAP_CFG1_GET_CFG1(val64);
307 val64 = vxge_os_pio_mem_read64(pdev, regh0,
310 vpath_reg = (vxge_hal_vpath_reg_t *) ((void *)(bar0 + val64));
319 val64 = vxge_os_pio_mem_read64(pdev, regh0,
322 mrpcim_reg = (vxge_hal_mrpcim_reg_t *) ((void *)(bar0 + val64));
324 val64 = vxge_os_pio_mem_read64(pdev, regh0,
327 val64 |= VXGE_HAL_SW_RESET_CFG1_TYPE;
330 val64,
499 u64 val64;
534 val64 = VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_ONE |
546 val64,
566 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
570 *data = (u16) VXGE_HAL_MDIO_MGR_ACCESS_GET_PORT_DATA(val64);
594 u64 val64;
791 val64 = VXGE_HAL_INI_ERRORS_REG_DCPL_FSM_ERR |
796 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->ini_errors_mask);
798 val64 = VXGE_HAL_DMA_ERRORS_REG_RDARB_FSM_ERR |
824 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->dma_errors_mask);
826 val64 = VXGE_HAL_TGT_ERRORS_REG_TGT_REQ_FSM_ERR |
829 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tgt_errors_mask);
831 val64 = VXGE_HAL_CONFIG_ERRORS_REG_I2C_MAIN_FSM_ERR |
842 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
845 val64 = VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_FSM_ERR |
854 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->crdt_errors_mask);
856 val64 = VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_STATSB_FSM_ERR |
870 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
873 val64 = VXGE_HAL_PLL_ERRORS_REG_CORE_CMG_PLL_OOL |
877 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pll_errors_mask);
879 val64 = VXGE_HAL_MRPCIM_PPIF_INT_STATUS_INI_ERRORS_INI_INT |
887 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
890 val64 = VXGE_HAL_DBECC_ERR_REG_PCI_RETRY_BUF_DB_ERR |
897 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->dbecc_err_mask);
899 val64 = VXGE_HAL_GENERAL_ERR_REG_PCI_LINK_RST_FSM_ERR;
901 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->general_err_mask);
903 val64 = VXGE_HAL_PCIPIF_INT_STATUS_DBECC_ERR_DBECC_ERR_INT |
906 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pcipif_int_mask);
908 val64 = VXGE_HAL_PDA_ALARM_REG_PDA_SM_ERR;
910 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pda_alarm_mask);
912 val64 = 0;
915 val64 |= VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FRM_BUF_DBE(i) |
921 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pcc_error_mask);
923 val64 = 0;
926 val64 |= VXGE_HAL_LSO_ERROR_REG_PCC_LSO_FSM_ERR_ALARM(i);
929 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->lso_error_mask);
931 val64 = VXGE_HAL_SM_ERROR_REG_SM_FSM_ERR_ALARM;
933 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->sm_error_mask);
935 val64 = VXGE_HAL_RTDMA_INT_STATUS_PDA_ALARM_PDA_INT |
940 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rtdma_int_mask);
942 val64 = VXGE_HAL_RC_ALARM_REG_FTC_SM_ERR |
953 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rc_alarm_mask);
955 val64 = 0;
958 val64 |= VXGE_HAL_RXDRM_SM_ERR_REG_PRC_VP(i);
961 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rxdrm_sm_err_mask);
963 val64 = 0;
966 val64 |= VXGE_HAL_RXDCM_SM_ERR_REG_PRC_VP(i);
969 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rxdcm_sm_err_mask);
971 val64 = 0;
974 val64 |= VXGE_HAL_RXDWM_SM_ERR_REG_PRC_VP(i);
977 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rxdwm_sm_err_mask);
979 val64 = VXGE_HAL_RDA_ERR_REG_RDA_SM0_ERR_ALARM |
986 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rda_err_mask);
988 val64 = 0;
991 val64 |= VXGE_HAL_RDA_ECC_DB_REG_RDA_RXD_ERR(i);
994 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rda_ecc_db_mask);
996 val64 = VXGE_HAL_RQA_ERR_REG_RQA_SM_ERR_ALARM;
998 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rqa_err_mask);
1000 val64 = 0;
1003 val64 |= VXGE_HAL_FRF_ALARM_REG_PRC_VP_FRF_SM_ERR(i);
1006 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->frf_alarm_mask);
1008 val64 = VXGE_HAL_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_DB |
1015 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rocrc_alarm_mask);
1017 val64 = VXGE_HAL_WDE0_ALARM_REG_WDE0_DCC_SM_ERR |
1023 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wde0_alarm_mask);
1025 val64 = VXGE_HAL_WDE1_ALARM_REG_WDE1_DCC_SM_ERR |
1031 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wde1_alarm_mask);
1033 val64 = VXGE_HAL_WDE2_ALARM_REG_WDE2_DCC_SM_ERR |
1039 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wde2_alarm_mask);
1041 val64 = VXGE_HAL_WDE3_ALARM_REG_WDE3_DCC_SM_ERR |
1047 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wde3_alarm_mask);
1049 val64 = VXGE_HAL_WRDMA_INT_STATUS_RC_ALARM_RC_INT |
1062 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wrdma_int_mask);
1064 val64 = VXGE_HAL_G3CMCT_ERR_REG_G3IF_SM_ERR |
1069 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->g3cmct_err_mask);
1071 val64 = VXGE_HAL_G3CMCT_INT_STATUS_ERR_G3IF_INT;
1073 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->g3cmct_int_mask);
1075 val64 = VXGE_HAL_GSSCC_ERR_REG_SSCC_SSR_DB_ERR(0x3) |
1080 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gsscc_err_mask);
1084 val64 = VXGE_HAL_GSSC_ERR0_REG_SSCC_STATE_DB_ERR(0xff) |
1089 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
1092 val64 = VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_DB_ERR |
1113 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
1118 val64 = VXGE_HAL_GCMG1_INT_STATUS_GSSCC_ERR_GSSCC_INT |
1126 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gcmg1_int_mask);
1128 val64 = VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_MEM_DB_ERR(0xf) |
1157 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gxtmc_err_mask);
1159 val64 = VXGE_HAL_GCP_ERR_REG_CP_H2L2CP_FIFO_ERR |
1164 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gcp_err_mask);
1166 val64 = VXGE_HAL_CMC_ERR_REG_CMC_CMC_SM_ERR;
1168 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->cmc_err_mask);
1170 val64 = VXGE_HAL_GCMG2_INT_STATUS_GXTMC_ERR_GXTMC_INT |
1174 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gcmg2_int_mask);
1176 val64 = VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_SM_ERR;
1178 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
1181 val64 = VXGE_HAL_G3IFCMD_CML_INT_STATUS_ERR_G3IF_INT;
1183 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
1186 val64 = VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_SM_ERR;
1188 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
1191 val64 = VXGE_HAL_G3IFCMD_CMU_INT_STATUS_ERR_G3IF_INT;
1193 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
1196 val64 = VXGE_HAL_PSSCC_ERR_REG_SSCC_CP2STE_OFLOW_ERR |
1199 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
1202 val64 = VXGE_HAL_PCMG1_INT_STATUS_PSSCC_ERR_PSSCC_INT;
1204 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
1207 val64 = VXGE_HAL_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_DB_ERR(0x3) |
1254 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pxtmc_err_mask);
1256 val64 = VXGE_HAL_CP_EXC_REG_CP_CP_CAUSE_CRIT_INT |
1259 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->cp_exc_mask);
1261 val64 = VXGE_HAL_CP_ERR_REG_CP_CP_DCACHE_DB_ERR(0xff) |
1285 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->cp_err_mask);
1287 val64 = VXGE_HAL_PCMG2_INT_STATUS_PXTMC_ERR_PXTMC_INT |
1291 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pcmg2_int_mask);
1293 val64 = VXGE_HAL_DAM_ERR_REG_DAM_RDSB_ECC_DB_ERR |
1306 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->dam_err_mask);
1308 val64 = VXGE_HAL_PCMG3_INT_STATUS_DAM_ERR_DAM_INT;
1310 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pcmg3_int_mask);
1312 val64 = VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR(0x3) |
1319 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->xmac_gen_err_mask);
1321 val64 = VXGE_HAL_XGXS_GEN_ERR_REG_XGXS_XGXS_FSM_ERR;
1323 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->xgxs_gen_err_mask);
1325 val64 = VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_DOWN |
1332 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
1335 val64 = VXGE_HAL_XGMAC_INT_STATUS_XMAC_GEN_ERR_XMAC_GEN_INT |
1339 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->xgmac_int_mask);
1341 val64 =
1355 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
1358 val64 = VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT0_FSM_ERR |
1363 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
1366 val64 = VXGE_HAL_RXMAC_INT_STATUS_RXMAC_ECC_ERR_RXMAC_ECC_INT |
1369 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rxmac_int_mask);
1371 val64 = VXGE_HAL_TXMAC_GEN_ERR_REG_TMACJ_PERMANENT_STOP;
1373 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
1376 val64 = VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_DB_ERR |
1384 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
1387 val64 = VXGE_HAL_TMAC_INT_STATUS_TXMAC_GEN_ERR_TXMAC_GEN_INT |
1390 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tmac_int_mask);
1392 val64 = VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_SM_ERR;
1394 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
1397 val64 = VXGE_HAL_G3IFCMD_FB_INT_STATUS_ERR_G3IF_INT;
1399 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64,
1402 val64 = VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_A |
1409 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->mc_err_mask);
1411 val64 = VXGE_HAL_GROCRC_ALARM_REG_XFMD_WR_FIFO_ERR |
1414 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->grocrc_alarm_mask);
1416 val64 = VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_DB_ERR |
1425 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->fau_ecc_err_mask);
1427 val64 = VXGE_HAL_MC_INT_STATUS_MC_ERR_MC_INT |
1431 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->mc_int_mask);
1433 val64 = VXGE_HAL_G3FBCT_ERR_REG_G3IF_SM_ERR |
1438 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->g3fbct_err_mask);
1440 val64 = VXGE_HAL_G3FBCT_INT_STATUS_ERR_G3IF_INT;
1442 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->g3fbct_int_mask);
1444 val64 = VXGE_HAL_ORP_ERR_REG_ORP_FIFO_DB_ERR |
1456 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->orp_err_mask);
1458 val64 = VXGE_HAL_PTM_ALARM_REG_PTM_RDCTRL_SYNC_ERR |
1464 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->ptm_alarm_mask);
1466 val64 = VXGE_HAL_TPA_ERROR_REG_TPA_FSM_ERR_ALARM |
1469 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tpa_error_mask);
1471 val64 = VXGE_HAL_TPA_INT_STATUS_ORP_ERR_ORP_INT |
1475 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tpa_int_mask);
1477 val64 = VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_ECC_DB_ERR |
1480 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->kdfc_err_mask);
1482 val64 = VXGE_HAL_DOORBELL_INT_STATUS_KDFC_ERR_REG_TXDMA_KDFC_INT;
1484 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->doorbell_int_mask);
1486 val64 = VXGE_HAL_TIM_ERR_REG_TIM_VBLS_DB_ERR |
1496 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tim_err_mask);
1498 val64 = VXGE_HAL_MSG_EXC_REG_MP_MXP_CAUSE_CRIT_INT |
1503 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_exc_mask);
1505 val64 = VXGE_HAL_MSG_ERR_REG_UP_UXP_WAKE_FSM_INTEGRITY_ERR |
1540 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_err_mask);
1542 val64 =
1581 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_err2_mask);
1583 val64 = VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR0 |
1604 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_err3_mask);
1606 val64 = VXGE_HAL_MSG_INT_STATUS_TIM_ERR_TIM_INT |
1612 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_int_mask);
1614 val64 = VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PIC_INT |
1639 (u32) bVAL32(~val64, 0),
1879 u64 val64;
1918 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
1922 val64 |= VXGE_HAL_SW_RESET_CFG1_TYPE;
1926 val64,
1962 u64 val64;
2026 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
2031 (u32) VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(val64);
2033 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
2038 (u32) VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(val64);
2040 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
2045 (u32) VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(val64);
2047 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
2052 (u32) VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(val64);
2340 u64 val64;
2368 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
2372 val64 |= VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE;
2376 val64,
2379 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
2383 val64 |= VXGE_HAL_STATS_CFG0_STATS_ENABLE(
2388 (u32) bVAL32(val64, 0),
2414 u64 val64;
2435 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
2439 val64 &= ~VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE;
2443 val64,
2465 u64 val64;
2498 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
2502 val64 &= ~VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE;
2506 val64,
2541 u64 val64;
2562 val64 = VXGE_HAL_XMAC_STATS_SYS_CMD_OP(operation) |
2570 (u32) bVAL32(val64, 32),
2577 (u32) bVAL32(val64, 0),
2618 u64 val64;
2643 VXGE_HAL_STATS_GET_AGGRn_TX_FRMS(val64);
2649 VXGE_HAL_STATS_GET_AGGRn_TX_DATA_OCTETS(val64);
2655 VXGE_HAL_STATS_GET_AGGRn_TX_MCAST_FRMS(val64);
2661 VXGE_HAL_STATS_GET_AGGRn_TX_BCAST_FRMS(val64);
2667 VXGE_HAL_STATS_GET_AGGRn_TX_DISCARDED_FRMS(val64);
2673 VXGE_HAL_STATS_GET_AGGRn_TX_ERRORED_FRMS(val64);
2679 VXGE_HAL_STATS_GET_AGGRn_RX_FRMS(val64);
2685 VXGE_HAL_STATS_GET_AGGRn_RX_DATA_OCTETS(val64);
2691 VXGE_HAL_STATS_GET_AGGRn_RX_MCAST_FRMS(val64);
2697 VXGE_HAL_STATS_GET_AGGRn_RX_BCAST_FRMS(val64);
2703 VXGE_HAL_STATS_GET_AGGRn_RX_DISCARDED_FRMS(val64);
2709 VXGE_HAL_STATS_GET_AGGRn_RX_ERRORED_FRMS(val64);
2715 VXGE_HAL_STATS_GET_AGGRn_RX_U_SLOW_PROTO_FRMS(val64);
2737 u64 val64;
2762 VXGE_HAL_STATS_GET_PORTn_TX_TTL_FRMS(val64);
2768 VXGE_HAL_STATS_GET_PORTn_TX_TTL_OCTETS(val64);
2774 VXGE_HAL_STATS_GET_PORTn_TX_DATA_OCTETS(val64);
2780 VXGE_HAL_STATS_GET_PORTn_TX_MCAST_FRMS(val64);
2786 VXGE_HAL_STATS_GET_PORTn_TX_BCAST_FRMS(val64);
2792 VXGE_HAL_STATS_GET_PORTn_TX_UCAST_FRMS(val64);
2798 VXGE_HAL_STATS_GET_PORTn_TX_TAGGED_FRMS(val64);
2804 VXGE_HAL_STATS_GET_PORTn_TX_VLD_IP(val64);
2810 VXGE_HAL_STATS_GET_PORTn_TX_VLD_IP_OCTETS(val64);
2816 VXGE_HAL_STATS_GET_PORTn_TX_ICMP(val64);
2822 VXGE_HAL_STATS_GET_PORTn_TX_TCP(val64);
2828 VXGE_HAL_STATS_GET_PORTn_TX_RST_TCP(val64);
2834 VXGE_HAL_STATS_GET_PORTn_TX_UDP(val64);
2840 (u32) VXGE_HAL_STATS_GET_PORTn_TX_UNKNOWN_PROTOCOL(val64);
2846 (u32) VXGE_HAL_STATS_GET_PORTn_TX_PARSE_ERROR(val64);
2852 VXGE_HAL_STATS_GET_PORTn_TX_PAUSE_CTRL_FRMS(val64);
2858 (u32) VXGE_HAL_STATS_GET_PORTn_TX_LACPDU_FRMS(val64);
2864 (u32) VXGE_HAL_STATS_GET_PORTn_TX_MRKR_PDU_FRMS(val64);
2870 (u32) VXGE_HAL_STATS_GET_PORTn_TX_MRKR_RESP_PDU_FRMS(val64);
2876 (u32) VXGE_HAL_STATS_GET_PORTn_TX_DROP_IP(val64);
2882 (u32) VXGE_HAL_STATS_GET_PORTn_TX_XGMII_CHAR1_MATCH(val64);
2888 (u32) VXGE_HAL_STATS_GET_PORTn_TX_XGMII_CHAR2_MATCH(val64);
2894 (u32) VXGE_HAL_STATS_GET_PORTn_TX_XGMII_COL1_MATCH(val64);
2900 (u32) VXGE_HAL_STATS_GET_PORTn_TX_XGMII_COL2_MATCH(val64);
2906 (u16) VXGE_HAL_STATS_GET_PORTn_TX_DROP_FRMS(val64);
2912 (u16) VXGE_HAL_STATS_GET_PORTn_TX_ANY_ERR_FRMS(val64);
2918 VXGE_HAL_STATS_GET_PORTn_RX_TTL_FRMS(val64);
2924 VXGE_HAL_STATS_GET_PORTn_RX_VLD_FRMS(val64);
2930 VXGE_HAL_STATS_GET_PORTn_RX_OFFLOAD_FRMS(val64);
2936 VXGE_HAL_STATS_GET_PORTn_RX_TTL_OCTETS(val64);
2942 VXGE_HAL_STATS_GET_PORTn_RX_DATA_OCTETS(val64);
2948 VXGE_HAL_STATS_GET_PORTn_RX_OFFLOAD_OCTETS(val64);
2954 VXGE_HAL_STATS_GET_PORTn_RX_VLD_MCAST_FRMS(val64);
2960 VXGE_HAL_STATS_GET_PORTn_RX_VLD_BCAST_FRMS(val64);
2966 VXGE_HAL_STATS_GET_PORTn_RX_ACC_UCAST_FRMS(val64);
2972 VXGE_HAL_STATS_GET_PORTn_RX_ACC_NUCAST_FRMS(val64);
2978 VXGE_HAL_STATS_GET_PORTn_RX_TAGGED_FRMS(val64);
2984 VXGE_HAL_STATS_GET_PORTn_RX_LONG_FRMS(val64);
2990 VXGE_HAL_STATS_GET_PORTn_RX_USIZED_FRMS(val64);
2996 VXGE_HAL_STATS_GET_PORTn_RX_OSIZED_FRMS(val64);
3002 VXGE_HAL_STATS_GET_PORTn_RX_FRAG_FRMS(val64);
3008 VXGE_HAL_STATS_GET_PORTn_RX_JABBER_FRMS(val64);
3014 VXGE_HAL_STATS_GET_PORTn_RX_TTL_64_FRMS(val64);
3020 VXGE_HAL_STATS_GET_PORTn_RX_TTL_65_127_FRMS(val64);
3026 VXGE_HAL_STATS_GET_PORTn_RX_TTL_128_255_FRMS(val64);
3032 VXGE_HAL_STATS_GET_PORTn_RX_TTL_256_511_FRMS(val64);
3038 VXGE_HAL_STATS_GET_PORTn_RX_TTL_512_1023_FRMS(val64);
3044 VXGE_HAL_STATS_GET_PORTn_RX_TTL_1024_1518_FRMS(val64);
3050 VXGE_HAL_STATS_GET_PORTn_RX_TTL_1519_4095_FRMS(val64);
3056 VXGE_HAL_STATS_GET_PORTn_RX_TTL_4096_8191_FRMS(val64);
3062 VXGE_HAL_STATS_GET_PORTn_RX_TTL_8192_MAX_FRMS(val64);
3068 VXGE_HAL_STATS_GET_PORTn_RX_TTL_GT_MAX_FRMS(val64);
3073 port_stats->rx_ip = VXGE_HAL_STATS_GET_PORTn_RX_IP(val64);
3079 VXGE_HAL_STATS_GET_PORTn_RX_ACC_IP(val64);
3085 VXGE_HAL_STATS_GET_PORTn_RX_IP_OCTETS(val64);
3091 VXGE_HAL_STATS_GET_PORTn_RX_ERR_IP(val64);
3096 port_stats->rx_icmp = VXGE_HAL_STATS_GET_PORTn_RX_ICMP(val64);
3101 port_stats->rx_tcp = VXGE_HAL_STATS_GET_PORTn_RX_TCP(val64);
3106 port_stats->rx_udp = VXGE_HAL_STATS_GET_PORTn_RX_UDP(val64);
3111 port_stats->rx_err_tcp = VXGE_HAL_STATS_GET_PORTn_RX_ERR_TCP(val64);
3117 VXGE_HAL_STATS_GET_PORTn_RX_PAUSE_CNT(val64);
3123 VXGE_HAL_STATS_GET_PORTn_RX_PAUSE_CTRL_FRMS(val64);
3129 VXGE_HAL_STATS_GET_PORTn_RX_UNSUP_CTRL_FRMS(val64);
3135 VXGE_HAL_STATS_GET_PORTn_RX_FCS_ERR_FRMS(val64);
3141 VXGE_HAL_STATS_GET_PORTn_RX_IN_RNG_LEN_ERR_FRMS(val64);
3147 VXGE_HAL_STATS_GET_PORTn_RX_OUT_RNG_LEN_ERR_FRMS(val64);
3153 VXGE_HAL_STATS_GET_PORTn_RX_DROP_FRMS(val64);
3159 VXGE_HAL_STATS_GET_PORTn_RX_DISCARDED_FRMS(val64);
3165 VXGE_HAL_STATS_GET_PORTn_RX_DROP_IP(val64);
3171 VXGE_HAL_STATS_GET_PORTn_RX_DRP_UDP(val64);
3177 (u32) VXGE_HAL_STATS_GET_PORTn_RX_LACPDU_FRMS(val64);
3183 (u32) VXGE_HAL_STATS_GET_PORTn_RX_MRKR_PDU_FRMS(val64);
3189 (u32) VXGE_HAL_STATS_GET_PORTn_RX_MRKR_RESP_PDU_FRMS(val64);
3195 (u32) VXGE_HAL_STATS_GET_PORTn_RX_UNKNOWN_PDU_FRMS(val64);
3201 (u32) VXGE_HAL_STATS_GET_PORTn_RX_ILLEGAL_PDU_FRMS(val64);
3207 (u32) VXGE_HAL_STATS_GET_PORTn_RX_FCS_DISCARD(val64);
3213 (u32) VXGE_HAL_STATS_GET_PORTn_RX_LEN_DISCARD(val64);
3219 (u32) VXGE_HAL_STATS_GET_PORTn_RX_SWITCH_DISCARD(val64);
3225 (u32) VXGE_HAL_STATS_GET_PORTn_RX_L2_MGMT_DISCARD(val64);
3231 (u32) VXGE_HAL_STATS_GET_PORTn_RX_RPA_DISCARD(val64);
3237 (u32) VXGE_HAL_STATS_GET_PORTn_RX_TRASH_DISCARD(val64);
3243 (u32) VXGE_HAL_STATS_GET_PORTn_RX_RTS_DISCARD(val64);
3249 (u32) VXGE_HAL_STATS_GET_PORTn_RX_RED_DISCARD(val64);
3255 (u32) VXGE_HAL_STATS_GET_PORTn_RX_BUFF_FULL_DISCARD(val64);
3261 (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_DATA_ERR_CNT(val64);
3267 (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_CTRL_ERR_CNT(val64);
3273 (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_ERR_SYM(val64);
3279 (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_CHAR1_MATCH(val64);
3285 (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_CHAR2_MATCH(val64);
3291 (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_COL1_MATCH(val64);
3297 (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_COL2_MATCH(val64);
3303 (u32) VXGE_HAL_STATS_GET_PORTn_RX_LOCAL_FAULT(val64);
3309 (u32) VXGE_HAL_STATS_GET_PORTn_RX_REMOTE_FAULT(val64);
3315 (u32) VXGE_HAL_STATS_GET_PORTn_RX_JETTISON(val64);
3412 u64 val64;
3425 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3430 (u32) VXGE_HAL_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP(val64);
3433 (u32) VXGE_HAL_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP(val64);
3436 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3443 val64);
3445 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3452 val64);
3454 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3461 val64);
3464 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3469 (u32) VXGE_HAL_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP(val64);
3472 (u32) VXGE_HAL_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP(val64);
3474 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3479 (u32) VXGE_HAL_GENSTATS_COUNT01_GET_GENSTATS_COUNT0(val64);
3482 (u32) VXGE_HAL_GENSTATS_COUNT01_GET_GENSTATS_COUNT1(val64);
3484 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3489 (u32) VXGE_HAL_GENSTATS_COUNT23_GET_GENSTATS_COUNT2(val64);
3492 (u32) VXGE_HAL_GENSTATS_COUNT23_GET_GENSTATS_COUNT3(val64);
3494 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3499 (u32) VXGE_HAL_GENSTATS_COUNT4_GET_GENSTATS_COUNT4(val64);
3501 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3506 (u32) VXGE_HAL_GENSTATS_COUNT5_GET_GENSTATS_COUNT5(val64);
3508 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3513 (u32) VXGE_HAL_DEBUG_STATS0_GET_RSTDROP_CPL(val64);
3516 (u32) VXGE_HAL_DEBUG_STATS0_GET_RSTDROP_MSG(val64);
3518 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3523 (u32) VXGE_HAL_DEBUG_STATS1_GET_RSTDROP_CLIENT0(val64);
3526 (u32) VXGE_HAL_DEBUG_STATS1_GET_RSTDROP_CLIENT1(val64);
3528 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3533 (u32) VXGE_HAL_DEBUG_STATS2_GET_RSTDROP_CLIENT2(val64);
3536 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3541 (u16) VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH(val64);
3544 (u16) VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_NPH(val64);
3547 (u16) VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_PH(val64);
3549 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3554 (u16) VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD(val64);
3557 (u16) VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_NPD(val64);
3560 (u16) VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_PD(val64);
3601 VXGE_HAL_STATS_GET_GLOBAL_PROG_EVENT_GNUM0(val64);
3607 VXGE_HAL_STATS_GET_GLOBAL_PROG_EVENT_GNUM1(val64);
3609 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3614 VXGE_HAL_ORP_LRO_EVENTS_GET_ORP_LRO_EVENTS(val64);
3616 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3621 VXGE_HAL_ORP_BS_EVENTS_GET_ORP_BS_EVENTS(val64);
3623 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3628 VXGE_HAL_ORP_IWARP_EVENTS_GET_ORP_IWARP_EVENTS(val64);
3630 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3635 (u32) VXGE_HAL_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS(val64);
3637 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3642 (u8) VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS(val64);
3645 (u8) VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS(val64);
3648 (u8) VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS(val64);
3650 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3655 (u8) VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS(val64);
3658 (u8) VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS(val64);
3661 (u8) VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS(val64);
3784 u64 val64;
3804 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3808 if (val64 & VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN) {
3820 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3824 if (val64 & VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN) {
3836 val64 = 0;
3838 val64 = VXGE_HAL_XGMAC_MAIN_CFG_PORT_PORT_EN;
3842 val64,
3845 if (!val64)
3848 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3853 val64 |= VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN;
3855 val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN;
3860 val64 |= VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS;
3862 val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS;
3868 val64 |= VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM;
3870 val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM;
3876 val64 &=
3879 val64 |= VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN(
3886 val64,
3889 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3896 val64 |= VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN;
3898 val64 &= ~VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN;
3903 val64,
3906 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3913 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN;
3915 val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN;
3922 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN;
3924 val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN;
3930 val64 &=
3933 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(
3941 val64 |=
3944 val64 &=
3951 val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(0xff);
3953 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(
3960 val64,
3963 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3969 val64 &=
3972 val64 |= VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(
3978 val64,
3981 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
3987 val64 &=
3991 val64 |= VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_UP(
3999 val64 &=
4003 val64 |= VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_UP(
4011 val64,
4014 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4019 val64 |= VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN;
4021 val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN;
4026 val64 |= VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD;
4028 val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD;
4033 val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE(0xff);
4035 val64 |= VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE(
4041 val64,
4044 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4050 val64 &=
4053 val64 |= VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(
4059 val64,
4062 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4069 val64 &= ~VXGE_HAL_RATEMGMT_CFG_PORT_MODE(0x3);
4071 val64 |= VXGE_HAL_RATEMGMT_CFG_PORT_MODE(
4079 val64 |= VXGE_HAL_RATEMGMT_CFG_PORT_RATE;
4081 val64 &= ~VXGE_HAL_RATEMGMT_CFG_PORT_RATE;
4089 val64 |=
4092 val64 &=
4101 val64 |=
4104 val64 &=
4113 val64 |=
4116 val64 &=
4123 val64,
4130 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4135 if (val64 & VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN) {
4147 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4152 if (val64 & VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN) {
4165 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4171 val64 |= VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN;
4173 val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN;
4178 val64 |= VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS;
4180 val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS;
4186 val64 |= VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM;
4188 val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM;
4194 val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN(0x3fff);
4196 val64 |= VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN(
4203 val64,
4207 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4215 val64 |= VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN;
4217 val64 &= ~VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN;
4222 val64,
4226 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4234 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN;
4236 val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN;
4243 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN;
4245 val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN;
4251 val64 &=
4254 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(
4262 val64 |=
4265 val64 &=
4272 val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(0xff);
4274 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(
4281 val64,
4285 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4292 val64 &=
4295 val64 |= VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(
4301 val64,
4305 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4311 val64 |= VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN;
4313 val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN;
4318 val64 |= VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD;
4320 val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD;
4325 val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE(0xff);
4327 val64 |= VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE(
4333 val64,
4337 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4343 val64 &=
4346 val64 |= VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(
4352 val64,
4358 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4366 val64 |= VXGE_HAL_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN;
4368 val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN;
4376 val64 |= VXGE_HAL_TXMAC_GEN_CFG1_TX_SWITCH_DISABLE;
4378 val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_TX_SWITCH_DISABLE;
4386 val64 |= VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_SWITCH;
4388 val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_SWITCH;
4396 val64 |= VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_WIRE;
4398 val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_WIRE;
4406 val64 |= VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE;
4408 val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE;
4416 val64 |= VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH;
4418 val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH;
4426 val64 |= VXGE_HAL_TXMAC_GEN_CFG1_HOST_APPEND_FCS;
4428 val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_HOST_APPEND_FCS;
4434 val64,
4437 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4445 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR;
4447 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR;
4455 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N;
4457 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N;
4465 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO;
4467 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO;
4475 val64 |=
4478 val64 &=
4487 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING;
4489 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING;
4497 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN;
4499 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN;
4507 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE;
4509 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE;
4515 val64,
4518 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4526 val64 |= VXGE_HAL_FAU_PA_CFG_REPL_L4_COMP_CSUM;
4528 val64 &= ~VXGE_HAL_FAU_PA_CFG_REPL_L4_COMP_CSUM;
4536 val64 |= VXGE_HAL_FAU_PA_CFG_REPL_L3_INCL_CF;
4538 val64 &= ~VXGE_HAL_FAU_PA_CFG_REPL_L3_INCL_CF;
4546 val64 |= VXGE_HAL_FAU_PA_CFG_REPL_L3_COMP_CSUM;
4548 val64 &= ~VXGE_HAL_FAU_PA_CFG_REPL_L3_COMP_CSUM;
4554 val64,
4557 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4565 val64 |=
4568 val64 &=
4577 val64 |=
4580 val64 &=
4589 val64 |=
4592 val64 &=
4601 val64 |=
4604 val64 &=
4613 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF;
4615 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF;
4623 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG;
4625 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG;
4632 val64,
4635 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4642 val64 &= ~(VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(0xf) |
4645 val64 |= VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(
4654 val64,
4657 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4665 val64 |= VXGE_HAL_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N;
4667 val64 &= ~VXGE_HAL_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N;
4675 val64 |= VXGE_HAL_TPA_GLOBAL_CFG_ECC_ENABLE_N;
4677 val64 &= ~VXGE_HAL_TPA_GLOBAL_CFG_ECC_ENABLE_N;
4683 val64,
4702 u64 val64;
4718 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4724 if (val64 & VXGE_HAL_LAG_CFG_EN)
4733 if (val64 & VXGE_HAL_LAG_CFG_EN) {
4734 val64 &= ~VXGE_HAL_LAG_CFG_EN;
4737 val64,
4749 val64 &= ~VXGE_HAL_LAG_CFG_MODE(0x3);
4750 val64 |= VXGE_HAL_LAG_CFG_MODE(lag_config->lag_mode);
4752 lag_config->lag_mode = (u32) VXGE_HAL_LAG_CFG_GET_MODE(val64);
4759 val64 |= VXGE_HAL_LAG_CFG_TX_DISCARD_BEHAV;
4761 val64 &= ~VXGE_HAL_LAG_CFG_TX_DISCARD_BEHAV;
4768 val64 |= VXGE_HAL_LAG_CFG_RX_DISCARD_BEHAV;
4770 val64 &= ~VXGE_HAL_LAG_CFG_RX_DISCARD_BEHAV;
4777 val64 |= VXGE_HAL_LAG_CFG_PREF_INDIV_PORT_NUM;
4779 val64 &= ~VXGE_HAL_LAG_CFG_PREF_INDIV_PORT_NUM;
4784 val64,
4787 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4795 val64 |= VXGE_HAL_LAG_TX_CFG_INCR_TX_AGGR_STATS;
4797 val64 &= ~VXGE_HAL_LAG_TX_CFG_INCR_TX_AGGR_STATS;
4802 val64 &= ~VXGE_HAL_LAG_TX_CFG_DISTRIB_ALG_SEL(0x3);
4803 val64 |= VXGE_HAL_LAG_TX_CFG_DISTRIB_ALG_SEL(
4811 (u32) VXGE_HAL_LAG_TX_CFG_GET_DISTRIB_ALG_SEL(val64);
4822 val64 |= VXGE_HAL_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL;
4824 val64 &= ~VXGE_HAL_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL;
4829 val64 &= ~VXGE_HAL_LAG_TX_CFG_COLL_MAX_DELAY(0xffff);
4830 val64 |= VXGE_HAL_LAG_TX_CFG_DISTRIB_ALG_SEL(
4836 val64,
4839 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4847 val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY;
4849 val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY;
4856 val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES;
4858 val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES;
4865 val64 |=
4868 val64 &=
4876 val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK;
4878 val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK;
4885 val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN;
4887 val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN;
4892 val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT(
4894 val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT(
4900 val64,
4903 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4911 val64 |= VXGE_HAL_LAG_LACP_CFG_EN;
4913 val64 &= ~VXGE_HAL_LAG_LACP_CFG_EN;
4920 val64 |= VXGE_HAL_LAG_LACP_CFG_LACP_BEGIN;
4922 val64 &= ~VXGE_HAL_LAG_LACP_CFG_LACP_BEGIN;
4929 val64 |= VXGE_HAL_LAG_LACP_CFG_DISCARD_LACP;
4931 val64 &= ~VXGE_HAL_LAG_LACP_CFG_DISCARD_LACP;
4938 val64 |= VXGE_HAL_LAG_LACP_CFG_LIBERAL_LEN_CHK;
4940 val64 &= ~VXGE_HAL_LAG_LACP_CFG_LIBERAL_LEN_CHK;
4945 val64,
4948 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
4956 val64 |= VXGE_HAL_LAG_MARKER_CFG_GEN_RCVR_EN;
4958 val64 &= ~VXGE_HAL_LAG_MARKER_CFG_GEN_RCVR_EN;
4965 val64 |= VXGE_HAL_LAG_MARKER_CFG_RESP_EN;
4967 val64 &= ~VXGE_HAL_LAG_MARKER_CFG_RESP_EN;
4972 val64 &= ~VXGE_HAL_LAG_MARKER_CFG_RESP_TIMEOUT(0xffff);
4973 val64 |= VXGE_HAL_LAG_MARKER_CFG_RESP_TIMEOUT(
4979 val64 &= ~VXGE_HAL_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL(
4981 val64 |= VXGE_HAL_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL(
4989 val64 |= VXGE_HAL_LAG_MARKER_CFG_THROTTLE_MRKR_RESP;
4991 val64 &= ~VXGE_HAL_LAG_MARKER_CFG_THROTTLE_MRKR_RESP;
4996 val64,
5001 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5009 val64 |= VXGE_HAL_LAG_PORT_CFG_EN;
5011 val64 &= ~VXGE_HAL_LAG_PORT_CFG_EN;
5018 val64 |=
5021 val64 &=
5029 val64 |=
5032 val64 &=
5040 val64 |=
5043 val64 &=
5049 val64,
5052 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5058 val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM(
5060 val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM(
5066 val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI(
5068 val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI(
5074 val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G(
5076 val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G(
5082 val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G(
5084 val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G(
5090 val64,
5093 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5101 val64 |=
5104 val64 &=
5112 val64 |=
5115 val64 &=
5123 val64 |=
5126 val64 &=
5134 val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION;
5136 val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION;
5143 val64 |=
5146 val64 &=
5154 val64 |=
5157 val64 &=
5165 val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED;
5167 val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED;
5174 val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED;
5176 val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED;
5181 val64,
5184 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5190 val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI(
5192 val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI(
5198 val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_KEY(
5200 val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_KEY(
5206 val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM(
5208 val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM(
5214 val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI(
5216 val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI(
5222 val64,
5225 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5233 val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY;
5235 val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY;
5242 val64 |=
5245 val64 &=
5253 val64 |=
5256 val64 &=
5264 val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION;
5266 val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION;
5273 val64 |=
5276 val64 &=
5284 val64 |=
5287 val64 &=
5295 val64 |=
5298 val64 &=
5306 val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED;
5308 val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED;
5313 val64,
5316 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5329 val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR(
5331 val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR(
5337 val64,
5344 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5348 val64 &= ~VXGE_HAL_LAG_AGGR_ID_CFG_ID(0xffff);
5349 val64 |= VXGE_HAL_LAG_AGGR_ID_CFG_ID(
5354 val64,
5357 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5369 val64 &=
5371 val64 |= VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR(mac_addr);
5378 val64 |=
5381 val64 &=
5389 val64 |= VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR_SEL;
5391 val64 &= ~VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR_SEL;
5396 val64,
5401 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5405 val64 &= ~VXGE_HAL_LAG_AGGR_ADMIN_KEY_KEY(0xffff);
5406 val64 |= VXGE_HAL_LAG_AGGR_ADMIN_KEY_KEY(
5411 val64,
5417 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5421 val64 &= ~VXGE_HAL_LAG_SYS_CFG_SYS_PRI(0xffff);
5422 val64 |= VXGE_HAL_LAG_SYS_CFG_SYS_PRI(
5427 val64,
5431 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5443 val64 &= ~VXGE_HAL_LAG_SYS_ID_ADDR(0xffffffffffffULL);
5444 val64 |= VXGE_HAL_LAG_SYS_ID_ADDR(mac_addr);
5451 val64 |= VXGE_HAL_LAG_SYS_ID_USE_PORT_ADDR;
5453 val64 &= ~VXGE_HAL_LAG_SYS_ID_USE_PORT_ADDR;
5459 val64 |= VXGE_HAL_LAG_SYS_ID_ADDR_SEL;
5461 val64 &= ~VXGE_HAL_LAG_SYS_ID_ADDR_SEL;
5466 val64,
5470 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5476 val64 &= ~VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_KEY(0xffff);
5477 val64 |= VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_KEY(
5485 val64 |= VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR;
5487 val64 &= ~VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR;
5492 val64,
5495 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5500 val64 &= ~VXGE_HAL_LAG_TIMER_CFG_1_FAST_PER(0xffff);
5501 val64 |= VXGE_HAL_LAG_TIMER_CFG_1_FAST_PER(
5506 val64 &= ~VXGE_HAL_LAG_TIMER_CFG_1_SLOW_PER(0xffff);
5507 val64 |= VXGE_HAL_LAG_TIMER_CFG_1_SLOW_PER(
5512 val64 &= ~VXGE_HAL_LAG_TIMER_CFG_1_SHORT_TIMEOUT(0xffff);
5513 val64 |= VXGE_HAL_LAG_TIMER_CFG_1_SHORT_TIMEOUT(
5518 val64 &= ~VXGE_HAL_LAG_TIMER_CFG_1_LONG_TIMEOUT(0xffff);
5519 val64 |= VXGE_HAL_LAG_TIMER_CFG_1_LONG_TIMEOUT(
5525 val64,
5528 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
5533 val64 &= ~VXGE_HAL_LAG_TIMER_CFG_2_CHURN_DET(0xffff);
5534 val64 |= VXGE_HAL_LAG_TIMER_CFG_2_CHURN_DET(
5539 val64 &= ~VXGE_HAL_LAG_TIMER_CFG_2_AGGR_WAIT(0xffff);
5540 val64 |= VXGE_HAL_LAG_TIMER_CFG_2_AGGR_WAIT(
5546 val64 &= ~VXGE_HAL_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(0xffff);
5547 val64 |= VXGE_HAL_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(
5553 val64 &= ~VXGE_HAL_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(0xffff);
5554 val64 |= VXGE_HAL_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(
5560 val64,
5725 u64 val64;
5744 val64 = VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL(rts_table) |
5749 val64 = VXGE_HAL_RTS_MGR_STEER_CTRL_WE;
5759 val64 |= VXGE_HAL_RTS_MGR_STEER_CTRL_TABLE_SEL;
5764 (u32) bVAL32(val64, 32),
5771 (u32) bVAL32(val64, 0),
5790 val64 = vxge_os_pio_mem_read64(
5795 if ((val64 & VXGE_HAL_RTS_MGR_STEER_CTRL_RMACJ_STATUS) &&
6007 u64 val64;
6034 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6038 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG;
6042 val64,
6066 u64 val64;
6093 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6097 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG;
6101 val64,
6234 u64 val64;
6266 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, hldev->header.regh0,
6269 if (val64 & VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN)
6272 if (val64 & VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN)
6304 u64 val64;
6335 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, hldev->header.regh0,
6338 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN;
6340 val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN;
6342 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN;
6344 val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN;
6347 val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
6436 u64 val64;
6504 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6509 (u32) VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(val64);
6511 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6516 (u32) VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(val64);
6518 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6523 (u32) VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(val64);
6525 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6530 (u32) VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(val64);
6537 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6541 val64 &= ~VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH(0x1f);
6542 val64 |= VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH(
6547 val64,
6563 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
6568 val64 &= ~VXGE_HAL_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(0x3f);
6570 val64 |= VXGE_HAL_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(8);
6574 val64,