Lines Matching refs:x1
42 #define AT91_UDP_FRM_ERR (0x1 << 16) /* Frame Error */
43 #define AT91_UDP_FRM_OK (0x1 << 17) /* Frame OK */
46 #define AT91_UDP_GSTATE_ADDR (0x1 << 0) /* Addressed state */
47 #define AT91_UDP_GSTATE_CONFG (0x1 << 1) /* Configured */
48 #define AT91_UDP_GSTATE_ESR (0x1 << 2) /* Enable Send Resume */
49 #define AT91_UDP_GSTATE_RSM (0x1 << 3) /* A Resume Has Been Sent to
51 #define AT91_UDP_GSTATE_RMW (0x1 << 4) /* Remote Wake Up Enable */
55 #define AT91_UDP_FADDR_EN (0x1 << 8)/* Function Enable */
64 #define AT91_UDP_INT_EP(n) (0x1 <<(n))/* Endpoint "n" Interrupt */
65 #define AT91_UDP_INT_RXSUSP (0x1 << 8)/* USB Suspend Interrupt */
66 #define AT91_UDP_INT_RXRSM (0x1 << 9)/* USB Resume Interrupt */
67 #define AT91_UDP_INT_EXTRSM (0x1 << 10)/* USB External Resume Interrupt */
68 #define AT91_UDP_INT_SOFINT (0x1 << 11)/* USB Start Of frame Interrupt */
69 #define AT91_UDP_INT_END_BR (0x1 << 12)/* USB End Of Bus Reset Interrupt */
70 #define AT91_UDP_INT_WAKEUP (0x1 << 13)/* USB Resume Interrupt */
86 #define AT91_UDP_RST_EP(n) (0x1 << (n))/* Reset Endpoint "n" */
92 #define AT91_UDP_CSR_TXCOMP (0x1 << 0) /* Generates an IN packet with data
94 #define AT91_UDP_CSR_RX_DATA_BK0 (0x1 << 1) /* Receive Data Bank 0 */
95 #define AT91_UDP_CSR_RXSETUP (0x1 << 2) /* Sends STALL to the Host
97 #define AT91_UDP_CSR_ISOERROR (0x1 << 3) /* Isochronous error
99 #define AT91_UDP_CSR_STALLSENT (0x1 << 3) /* Stall sent (Control, bulk,
101 #define AT91_UDP_CSR_TXPKTRDY (0x1 << 4) /* Transmit Packet Ready */
102 #define AT91_UDP_CSR_FORCESTALL (0x1 << 5) /* Force Stall (used by
105 #define AT91_UDP_CSR_RX_DATA_BK1 (0x1 << 6) /* Receive Data Bank 1 (only
108 #define AT91_UDP_CSR_DIR (0x1 << 7) /* Transfer Direction */
111 #define AT91_UDP_CSR_ET_ISO (0x1 << 8) /* Isochronous */
116 #define AT91_UDP_CSR_DTGLE (0x1 << 11) /* Data Toggle */
117 #define AT91_UDP_CSR_EPEDS (0x1 << 15) /* Endpoint Enable Disable */
124 #define AT91_UDP_TXVC_DIS (0x1 << 8)