Lines Matching defs:mss
39 #include <dev/sound/isa/mss.h>
79 * mss codec type, etc. etc.
98 static int mss_detect(device_t dev, struct mss_info *mss);
100 static int opti_detect(device_t dev, struct mss_info *mss);
102 static char *ymf_test(device_t dev, struct mss_info *mss);
103 static void ad_unmute(struct mss_info *mss);
106 static int mss_mixer_set(struct mss_info *mss, int dev, int left, int right);
107 static int mss_set_recsrc(struct mss_info *mss, int mask);
110 static int ad_wait_init(struct mss_info *mss, int x);
111 static int ad_read(struct mss_info *mss, int reg);
112 static void ad_write(struct mss_info *mss, int reg, u_char data);
113 static void ad_write_cnt(struct mss_info *mss, int reg, u_short data);
114 static void ad_enter_MCE(struct mss_info *mss);
115 static void ad_leave_MCE(struct mss_info *mss);
118 static void opti_write(struct mss_info *mss, u_char reg,
121 static u_char opti_read(struct mss_info *mss, u_char reg);
123 static int opti_init(device_t dev, struct mss_info *mss);
126 static void conf_wr(struct mss_info *mss, u_char reg, u_char data);
127 static u_char conf_rd(struct mss_info *mss, u_char reg);
180 #define DV_F_TRUE_MSS 0x00010000 /* mss _with_ base regs */
185 mss_lock(struct mss_info *mss)
187 snd_mtxlock(mss->lock);
191 mss_unlock(struct mss_info *mss)
193 snd_mtxunlock(mss->lock);
217 io_rd(struct mss_info *mss, int reg)
219 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
220 return port_rd(mss->io_base, reg);
224 io_wr(struct mss_info *mss, int reg, u_int8_t data)
226 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4;
227 port_wr(mss->io_base, reg, data);
231 conf_wr(struct mss_info *mss, u_char reg, u_char value)
233 port_wr(mss->conf_base, 0, reg);
234 port_wr(mss->conf_base, 1, value);
238 conf_rd(struct mss_info *mss, u_char reg)
240 port_wr(mss->conf_base, 0, reg);
241 return port_rd(mss->conf_base, 1);
245 opti_wr(struct mss_info *mss, u_char reg, u_char value)
247 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
248 port_wr(mss->conf_base, mss->opti_offset + 1, value);
252 opti_rd(struct mss_info *mss, u_char reg)
254 port_wr(mss->conf_base, mss->opti_offset + 0, reg);
255 return port_rd(mss->conf_base, mss->opti_offset + 1);
259 gus_wr(struct mss_info *mss, u_char reg, u_char value)
261 port_wr(mss->conf_base, 3, reg);
262 port_wr(mss->conf_base, 5, value);
266 gus_rd(struct mss_info *mss, u_char reg)
268 port_wr(mss->conf_base, 3, reg);
269 return port_rd(mss->conf_base, 5);
273 mss_release_resources(struct mss_info *mss, device_t dev)
275 if (mss->irq) {
276 if (mss->ih)
277 bus_teardown_intr(dev, mss->irq, mss->ih);
278 bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid,
279 mss->irq);
280 mss->irq = 0;
282 if (mss->drq2) {
283 if (mss->drq2 != mss->drq1) {
284 isa_dma_release(rman_get_start(mss->drq2));
285 bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid,
286 mss->drq2);
288 mss->drq2 = 0;
290 if (mss->drq1) {
291 isa_dma_release(rman_get_start(mss->drq1));
292 bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid,
293 mss->drq1);
294 mss->drq1 = 0;
296 if (mss->io_base) {
297 bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid,
298 mss->io_base);
299 mss->io_base = 0;
301 if (mss->conf_base) {
302 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
303 mss->conf_base);
304 mss->conf_base = 0;
306 if (mss->indir) {
307 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid,
308 mss->indir);
309 mss->indir = 0;
311 if (mss->parent_dmat) {
312 bus_dma_tag_destroy(mss->parent_dmat);
313 mss->parent_dmat = 0;
315 if (mss->lock) snd_mtxfree(mss->lock);
317 free(mss, M_DEVBUF);
321 mss_alloc_resources(struct mss_info *mss, device_t dev)
324 if (!mss->io_base)
325 mss->io_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
326 &mss->io_rid, RF_ACTIVE);
327 if (!mss->irq)
328 mss->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
329 &mss->irq_rid, RF_ACTIVE);
330 if (!mss->drq1)
331 mss->drq1 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
332 &mss->drq1_rid,
334 if (mss->conf_rid >= 0 && !mss->conf_base)
335 mss->conf_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
336 &mss->conf_rid,
338 if (mss->drq2_rid >= 0 && !mss->drq2)
339 mss->drq2 = bus_alloc_resource_any(dev, SYS_RES_DRQ,
340 &mss->drq2_rid,
343 if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0;
344 if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0;
345 if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0;
348 pdma = rman_get_start(mss->drq1);
350 isa_dmainit(pdma, mss->bufsize);
351 mss->bd_flags &= ~BD_F_DUPLEX;
352 if (mss->drq2) {
353 rdma = rman_get_start(mss->drq2);
355 isa_dmainit(rdma, mss->bufsize);
356 mss->bd_flags |= BD_F_DUPLEX;
357 } else mss->drq2 = mss->drq1;
396 mss_set_recsrc(struct mss_info *mss, int mask)
420 ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev);
421 ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev);
427 mss_mixer_set(struct mss_info *mss, int dev, int left, int right)
433 switch (mss->bd_id) {
454 old = val = ad_read(mss, regoffs);
458 ad_write(mss, regoffs, val);
466 old = val = ad_read(mss, regoffs);
469 ad_write(mss, regoffs, val);
482 struct mss_info *mss = mix_getdevinfo(m);
486 switch(mss->bd_id) {
493 mss_lock(mss);
494 ad_write(mss, 20, 0x88);
495 ad_write(mss, 21, 0x88);
496 mss_unlock(mss);
506 mss_lock(mss);
507 ad_write(mss, 22, 0x88);
508 ad_write(mss, 23, 0x88);
509 mss_unlock(mss);
518 struct mss_info *mss = mix_getdevinfo(m);
520 mss_lock(mss);
521 mss_mixer_set(mss, dev, left, right);
522 mss_unlock(mss);
530 struct mss_info *mss = mix_getdevinfo(m);
532 mss_lock(mss);
533 src = mss_set_recsrc(mss, src);
534 mss_unlock(mss);
551 struct mss_info *mss = mix_getdevinfo(m);
557 mss_lock(mss);
558 conf_wr(mss, OPL3SAx_VOLUMEL, 7);
559 conf_wr(mss, OPL3SAx_VOLUMER, 7);
560 mss_unlock(mss);
568 struct mss_info *mss = mix_getdevinfo(m);
571 mss_lock(mss);
576 conf_wr(mss, OPL3SAx_VOLUMEL, t);
579 conf_wr(mss, OPL3SAx_VOLUMER, t);
586 conf_wr(mss, OPL3SAx_MIC, t);
593 conf_wr(mss, OPL3SAx_BASS, t);
600 conf_wr(mss, OPL3SAx_TREBLE, t);
604 mss_mixer_set(mss, dev, left, right);
606 mss_unlock(mss);
614 struct mss_info *mss = mix_getdevinfo(m);
615 mss_lock(mss);
616 src = mss_set_recsrc(mss, src);
617 mss_unlock(mss);
634 gusmax_setup(struct mss_info *mss, device_t dev, struct resource *alt)
675 port_wr(mss->conf_base, 2, 0);
677 port_wr(mss->conf_base, 2, 0);
683 mss_init(struct mss_info *mss, device_t dev)
689 mss->bd_flags |= BD_F_MCE_BIT;
690 switch(mss->bd_id) {
699 mss->opti_offset =
700 (rman_get_start(mss->conf_base) & ~3) + 2
701 - rman_get_start(mss->conf_base);
702 BVDDB(printf("mss_init: opti_offset=%d\n", mss->opti_offset));
703 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */
704 ad_write(mss, 10, 2); /* enable interrupts */
705 opti_wr(mss, 6, 2); /* MCIR6: mss enable, sb disable */
706 opti_wr(mss, 5, 0x28); /* MCIR5: codec in exp. mode,fifo */
711 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */
714 gus_wr(mss, 0x4c /* _URSTI */, 3);
726 if (mss->bd_id == MD_GUSMAX)
727 gusmax_setup(mss, dev, alt);
734 tmp = ad_read(mss, 0x0c);
735 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */
736 ad_write(mss, 0x19, 0); /* unmute left */
737 ad_write(mss, 0x1b, 0); /* unmute right */
738 ad_write(mss, 0x0c, tmp); /* restore old mode */
741 gus_wr(mss, 0x5a, 0x4f);
744 tmp = gus_rd(mss, 0x5b /* IVERI */);
745 gus_wr(mss, 0x5b, tmp | 1);
750 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */
751 r6 = conf_rd(mss, OPL3SAx_DMACONF);
752 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */
755 conf_wr(mss, OPL3SAx_VOLUMEL, 0);
756 conf_wr(mss, OPL3SAx_VOLUMER, 0);
757 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b);
760 if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931)
761 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */
762 ad_enter_MCE(mss);
763 ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4);
764 ad_leave_MCE(mss);
765 ad_write(mss, 10, 2); /* int enable */
766 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
768 ad_unmute(mss);
791 struct mss_info *mss = arg;
796 mss_lock(mss);
797 ad_read(mss, 11); /* fake read of status bits */
800 for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) {
802 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30;
804 if (sndbuf_runsz(mss->pch.buffer) && (c & 0x10)) {
806 mss_unlock(mss);
807 chn_intr(mss->pch.channel);
808 mss_lock(mss);
810 if (sndbuf_runsz(mss->rch.buffer) && (c & 0x20)) {
812 mss_unlock(mss);
813 chn_intr(mss->rch.channel);
814 mss_lock(mss);
817 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */
818 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
821 BVDDB(printf("mss_intr: irq, but not from mss\n"));
828 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */
830 mss_unlock(mss);
838 ad_wait_init(struct mss_info *mss, int x)
842 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10);
849 ad_read(struct mss_info *mss, int reg)
853 ad_wait_init(mss, 201000);
854 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
855 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
856 x = io_rd(mss, MSS_IDATA);
862 ad_write(struct mss_info *mss, int reg, u_char data)
867 ad_wait_init(mss, 1002000);
868 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK;
869 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x);
870 io_wr(mss, MSS_IDATA, data);
874 ad_write_cnt(struct mss_info *mss, int reg, u_short cnt)
876 ad_write(mss, reg+1, cnt & 0xff);
877 ad_write(mss, reg, cnt >> 8); /* upper base must be last */
881 wait_for_calibration(struct mss_info *mss)
893 t = ad_wait_init(mss, 1000000);
894 if (t & MSS_IDXBUSY) printf("mss: Auto calibration timed out(1).\n");
900 if (mss->bd_id == MD_GUSMAX || mss->bd_id == MD_GUSPNP) {
901 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--);
907 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100);
909 for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100);
913 ad_unmute(struct mss_info *mss)
915 ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE);
916 ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE);
920 ad_enter_MCE(struct mss_info *mss)
924 mss->bd_flags |= BD_F_MCE_BIT;
925 ad_wait_init(mss, 203000);
926 prev = io_rd(mss, MSS_INDEX);
928 io_wr(mss, MSS_INDEX, prev | MSS_MCE);
932 ad_leave_MCE(struct mss_info *mss)
936 if ((mss->bd_flags & BD_F_MCE_BIT) == 0) {
941 ad_wait_init(mss, 1000000);
943 mss->bd_flags &= ~BD_F_MCE_BIT;
945 prev = io_rd(mss, MSS_INDEX);
947 io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */
948 wait_for_calibration(mss);
954 struct mss_info *mss = ch->parent;
969 ad_enter_MCE(mss);
970 if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */
971 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */
972 ad_write(mss, 23, speed & 0xff); /* Speed LSB */
984 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel);
985 ad_wait_init(mss, 10000);
987 ad_leave_MCE(mss);
1003 struct mss_info *mss = ch->parent;
1023 ad_enter_MCE(mss);
1024 ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg);
1025 ad_wait_init(mss, 10000);
1026 if (ad_read(mss, 12) & 0x40) { /* mode2? */
1027 ad_write(mss, 28, arg); /* capture mode */
1028 ad_wait_init(mss, 10000);
1030 ad_leave_MCE(mss);
1037 struct mss_info *mss = ch->parent;
1046 m = ad_read(mss, 9);
1053 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt);
1065 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0);
1070 ad_write(mss, 9, m);
1071 if (ad_read(mss, 9) == m) break;
1074 m, ad_read(mss, 9)));
1086 struct mss_info *mss = (struct mss_info *)arg;
1092 reason = io_rd(mss, MSS_STATUS);
1094 DEB(printf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11)));
1098 mss_lock(mss);
1099 i11 = ad_read(mss, 11); /* XXX what's for ? */
1102 c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc;
1120 reason = io_rd(mss, MSS_STATUS);
1127 mss_unlock(mss);
1131 if (sndbuf_runsz(mss->rch.buffer) && (mc11 & 8)) {
1132 mss_unlock(mss);
1133 chn_intr(mss->rch.channel);
1134 mss_lock(mss);
1136 if (sndbuf_runsz(mss->pch.buffer) && (mc11 & 4)) {
1137 mss_unlock(mss);
1138 chn_intr(mss->pch.channel);
1139 mss_lock(mss);
1141 opti_wr(mss, 11, ~mc11); /* ack */
1143 mss_unlock(mss);
1152 struct mss_info *mss = devinfo;
1153 struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch;
1155 ch->parent = mss;
1159 if (sndbuf_alloc(ch->buffer, mss->parent_dmat, 0, mss->bufsize) != 0)
1161 sndbuf_dmasetup(ch->buffer, (dir == PCMDIR_PLAY)? mss->drq1 : mss->drq2);
1169 struct mss_info *mss = ch->parent;
1171 mss_lock(mss);
1173 mss_unlock(mss);
1181 struct mss_info *mss = ch->parent;
1184 mss_lock(mss);
1186 mss_unlock(mss);
1206 struct mss_info *mss = ch->parent;
1212 mss_lock(mss);
1214 mss_unlock(mss);
1280 struct mss_info *mss;
1284 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
1285 if (!mss) return ENXIO;
1287 mss->io_rid = 0;
1288 mss->conf_rid = -1;
1289 mss->irq_rid = 0;
1290 mss->drq1_rid = 0;
1291 mss->drq2_rid = -1;
1292 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
1294 if (!mss->io_base) {
1296 mss->io_rid = 0;
1299 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid,
1301 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid,
1304 if (!mss->io_base) goto no;
1320 tmpx = tmp = io_rd(mss, 3);
1329 rman_get_start(mss->io_base), tmpx));
1357 result = mss_detect(dev, mss);
1359 mss_release_resources(mss, dev);
1362 SYS_RES_IOPORT, mss->io_rid); /* XXX ? */
1368 mss_detect(device_t dev, struct mss_info *mss)
1374 if (mss->bd_id != 0) {
1375 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id,
1381 mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */
1384 if (opti_detect(dev, mss)) {
1385 switch (mss->bd_id) {
1394 if (opti_init(dev, mss) == 0) goto gotit;
1409 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000);
1422 ad_write(mss, 0, 0xaa);
1423 ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */
1424 tmp1 = ad_read(mss, 0);
1425 tmp2 = ad_read(mss, 1);
1431 ad_write(mss, 0, 0x45);
1432 ad_write(mss, 1, 0xaa);
1433 tmp1 = ad_read(mss, 0);
1434 tmp2 = ad_read(mss, 1);
1445 tmp = ad_read(mss, 12);
1446 ad_write(mss, 12, (~tmp) & 0x0f);
1447 tmp1 = ad_read(mss, 12);
1469 ad_write(mss, 12, 0); /* Mode2=disabled */
1472 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) {
1491 ad_write(mss, 12, 0x40); /* Set mode2, clear 0x80 */
1493 tmp1 = ad_read(mss, 12);
1503 ad_write(mss, 16, 0); /* Set I16 to known value */
1504 ad_write(mss, 0, 0x45);
1505 if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit;
1507 ad_write(mss, 0, 0xaa);
1508 if ((tmp1 = ad_read(mss, 16)) == 0xaa) { /* Rotten bits? */
1513 tmp1 = ad_read(mss, 25); /* Original bits */
1514 ad_write(mss, 25, ~tmp1); /* Invert all bits */
1515 if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) {
1520 mss->bd_id = MD_CS42XX;
1528 id = ad_read(mss, 25) & 0xe7;
1540 mss->bd_id = MD_CS42XX;
1545 mss->bd_id = MD_CS42XX;
1553 mss->bd_id = MD_CS42XX;
1564 tmp = ad_read(mss, 23);
1566 ad_write(mss, 23, ~tmp);
1567 if (ad_read(mss, 23) != tmp) { /* AD1845 ? */
1569 mss->bd_id = MD_AD1845;
1571 ad_write(mss, 23, tmp); /* Restore */
1573 yamaha = ymf_test(dev, mss);
1575 mss->bd_id = MD_YM0020;
1583 mss->bd_id = MD_CS42XX;
1588 mss->bd_id = MD_CS42XX;
1591 ad_write(mss, 25, tmp1); /* Restore bits */
1597 ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK)));
1605 opti_detect(device_t dev, struct mss_info *mss)
1619 mss->conf_rid = 3;
1620 mss->indir_rid = 4;
1622 mss->optibase = cards[c].base;
1623 mss->password = cards[c].password;
1624 mss->passwdreg = cards[c].passwdreg;
1625 mss->bd_id = cards[c].boardid;
1628 mss->indir = bus_alloc_resource(dev, SYS_RES_IOPORT,
1629 &mss->indir_rid, cards[c].indir_reg,
1632 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
1633 &mss->conf_rid, mss->optibase, mss->optibase+9,
1636 if (opti_read(mss, 1) != 0xff) {
1639 if (mss->indir)
1640 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, mss->indir);
1641 mss->indir = NULL;
1642 if (mss->conf_base)
1643 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, mss->conf_base);
1644 mss->conf_base = NULL;
1652 ymf_test(device_t dev, struct mss_info *mss)
1668 mss->conf_rid = 1;
1669 mss->conf_base = bus_alloc_resource(dev,
1671 &mss->conf_rid,
1674 if (!mss->conf_base) return 0;
1677 i = port_rd(mss->conf_base, 0);
1678 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF);
1679 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0;
1680 port_wr(mss->conf_base, 0, i);
1683 mss->conf_rid, mss->conf_base);
1686 bus_delete_resource(dev, SYS_RES_IOPORT, mss->conf_rid);
1688 mss->conf_base = 0;
1691 version = conf_rd(mss, OPL3SAx_MISC) & 0x07;
1698 mss_doattach(device_t dev, struct mss_info *mss)
1703 mss->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_mss softc");
1704 mss->bufsize = pcm_getbuffersize(dev, 4096, MSS_DEFAULT_BUFSZ, 65536);
1705 if (!mss_alloc_resources(mss, dev)) goto no;
1706 mss_init(mss, dev);
1707 pdma = rman_get_start(mss->drq1);
1708 rdma = rman_get_start(mss->drq2);
1722 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1)
1725 io_wr(mss, 0, bits | 0x40); /* config port */
1726 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n");
1738 io_wr(mss, 0, bits);
1739 printf("drq/irq conf %x\n", io_rd(mss, 0));
1741 mixer_init(dev, (mss->bd_id == MD_YM0020)? &ymmix_mixer_class : &mssmix_mixer_class, mss);
1742 switch (mss->bd_id) {
1744 snd_setup_intr(dev, mss->irq, 0, opti931_intr, mss, &mss->ih);
1747 snd_setup_intr(dev, mss->irq, 0, mss_intr, mss, &mss->ih);
1756 /*maxsize*/mss->bufsize, /*nsegments*/1,
1759 &mss->parent_dmat) != 0) {
1770 rman_get_start(mss->io_base), rman_get_start(mss->irq), pdma, status2, mss->bufsize);
1772 if (pcm_register(dev, mss, 1, 1)) goto no;
1773 pcm_addchan(dev, PCMDIR_REC, &msschan_class, mss);
1774 pcm_addchan(dev, PCMDIR_PLAY, &msschan_class, mss);
1779 mss_release_resources(mss, dev);
1787 struct mss_info *mss;
1793 mss = pcm_getdevinfo(dev);
1794 mss_release_resources(mss, dev);
1802 struct mss_info *mss;
1805 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
1806 if (!mss) return ENXIO;
1808 mss->io_rid = 0;
1809 mss->conf_rid = -1;
1810 mss->irq_rid = 0;
1811 mss->drq1_rid = 0;
1812 mss->drq2_rid = -1;
1816 mss->drq2_rid = 1;
1818 mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT;
1819 if (mss->bd_id == MD_YM0020) ymf_test(dev, mss);
1820 return mss_doattach(dev, mss);
1842 struct mss_info *mss;
1845 mss = pcm_getdevinfo(dev);
1847 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X) {
1850 ad_write(mss, i, mss->mss_indexed_regs[i]);
1852 conf_wr(mss, i, mss->opl_indexed_regs[i]);
1853 mss_intr(mss);
1856 if (mss->bd_id == MD_CS423X) {
1858 mss_lock(mss);
1859 mss_format(&mss->pch, mss->pch.channel->format);
1860 mss_speed(&mss->pch, mss->pch.channel->speed);
1861 mss_unlock(mss);
1881 struct mss_info *mss;
1883 mss = pcm_getdevinfo(dev);
1885 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X)
1888 conf_wr(mss, 0x12, 0x0c);
1890 mss->mss_indexed_regs[i] = ad_read(mss, i);
1892 mss->opl_indexed_regs[i] = conf_rd(mss, i);
1893 mss->opl_indexed_regs[0x12] = 0x0;
1920 azt2320_mss_mode(struct mss_info *mss, device_t dev)
1984 struct mss_info *mss;
1986 mss = malloc(sizeof(*mss), M_DEVBUF, M_WAITOK | M_ZERO);
1987 mss->io_rid = 0;
1988 mss->conf_rid = -1;
1989 mss->irq_rid = 0;
1990 mss->drq1_rid = 0;
1991 mss->drq2_rid = 1;
1992 mss->bd_id = MD_CS42XX;
1997 mss->bd_flags |= BD_F_MSS_OFFSET;
1998 mss->bd_id = MD_CS423X;
2002 mss->io_rid = 1;
2003 mss->conf_rid = 4;
2004 mss->bd_id = MD_YM0020;
2008 mss->io_rid = 1;
2009 mss->bd_id = MD_VIVO;
2013 mss->bd_flags |= BD_F_MSS_OFFSET;
2014 mss->conf_rid = 3;
2015 mss->bd_id = MD_OPTI931;
2019 mss->io_rid = 1;
2020 mss->conf_rid = 3;
2021 mss->bd_id = MD_OPTI925;
2025 mss->password = 0xe5;
2026 mss->passwdreg = 3;
2027 mss->optibase = 0xf0c;
2028 mss->io_rid = 2;
2029 mss->conf_rid = 3;
2030 mss->bd_id = MD_OPTI924;
2031 mss->bd_flags |= BD_F_924PNP;
2032 if(opti_init(dev, mss) != 0) {
2033 free(mss, M_DEVBUF);
2039 mss->io_rid = 1;
2044 if (azt2320_mss_mode(mss, dev) == -1) {
2045 free(mss, M_DEVBUF);
2049 mss->bd_flags |= BD_F_MSS_OFFSET;
2050 mss->io_rid = 2;
2055 mss->bd_flags |= BD_F_MSS_OFFSET;
2056 mss->io_rid = 2;
2057 mss->conf_rid = 1;
2058 mss->drq1_rid = 1;
2059 mss->drq2_rid = 0;
2060 mss->bd_id = MD_GUSPNP;
2064 mss->drq2_rid = -1;
2069 mss->bd_flags |= BD_F_MSS_OFFSET;
2072 return mss_doattach(dev, mss);
2076 opti_init(device_t dev, struct mss_info *mss)
2081 if (!mss->conf_base) {
2082 bus_set_resource(dev, SYS_RES_IOPORT, mss->conf_rid,
2083 mss->optibase, 0x9);
2085 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2086 &mss->conf_rid, mss->optibase, mss->optibase+0x9,
2090 if (!mss->conf_base)
2093 if (!mss->io_base)
2094 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2095 &mss->io_rid, 0, ~0, 8, RF_ACTIVE);
2097 if (!mss->io_base) /* No hint specified, use 0x530 */
2098 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT,
2099 &mss->io_rid, 0x530, 0x537, 8, RF_ACTIVE);
2101 if (!mss->io_base)
2104 switch (rman_get_start(mss->io_base)) {
2123 switch (mss->bd_id) {
2125 opti_write(mss, 1, 0x80 | basebits); /* MSS mode */
2126 opti_write(mss, 2, 0x00); /* Disable CD */
2127 opti_write(mss, 3, 0xf0); /* Disable SB IRQ */
2128 opti_write(mss, 4, 0xf0);
2129 opti_write(mss, 5, 0x00);
2130 opti_write(mss, 6, 0x02); /* MPU stuff */
2134 opti_write(mss, 1, 0x00 | basebits);
2135 opti_write(mss, 3, 0x00); /* Disable SB IRQ/DMA */
2136 opti_write(mss, 4, 0x52); /* Empty FIFO */
2137 opti_write(mss, 5, 0x3c); /* Mode 2 */
2138 opti_write(mss, 6, 0x02); /* Enable MSS */
2142 if (mss->bd_flags & BD_F_924PNP) {
2146 bus_set_resource(dev, SYS_RES_DRQ, mss->drq1_rid, drq, 1);
2150 mss->drq2_rid = 1;
2162 opti_write(struct mss_info *mss, u_char reg, u_char val)
2164 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2166 switch(mss->bd_id) {
2169 port_wr(mss->conf_base, mss->passwdreg, reg);
2170 port_wr(mss->conf_base, mss->passwdreg,
2171 mss->password);
2172 port_wr(mss->conf_base, 9, val);
2175 port_wr(mss->conf_base, reg, val);
2179 port_wr(mss->indir, 0, reg);
2180 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2181 port_wr(mss->indir, 1, val);
2188 opti_read(struct mss_info *mss, u_char reg)
2190 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2192 switch(mss->bd_id) {
2195 port_wr(mss->conf_base, mss->passwdreg, reg);
2196 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2197 return(port_rd(mss->conf_base, 9));
2199 return(port_rd(mss->conf_base, reg));
2203 port_wr(mss->indir, 0, reg);
2204 port_wr(mss->conf_base, mss->passwdreg, mss->password);
2205 return port_rd(mss->indir, 1);
2251 struct mss_info *mss;
2255 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO);
2256 if (mss == NULL)
2259 mss->bd_flags = BD_F_MSS_OFFSET;
2260 mss->io_rid = 2;
2261 mss->conf_rid = 1;
2262 mss->irq_rid = 0;
2263 mss->drq1_rid = 1;
2264 mss->drq2_rid = -1;
2267 mss->bd_id = MD_GUSMAX;
2269 mss->bd_id = MD_GUSPNP;
2270 mss->drq2_rid = 0;
2276 mss->drq2_rid = 0;
2278 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid,
2281 if (mss->conf_base == NULL) {
2282 mss_release_resources(mss, dev);
2294 port_wr(mss->conf_base, 6, ctl);
2297 return mss_doattach(dev, mss);