Lines Matching defs:val
176 smc_write_1(struct smc_softc *sc, bus_size_t offset, uint8_t val)
179 bus_write_1(sc->smc_reg, offset, val);
190 smc_write_2(struct smc_softc *sc, bus_size_t offset, uint16_t val)
193 bus_write_2(sc->smc_reg, offset, val);
224 uint16_t val;
245 val = bus_read_2(reg, BSR);
246 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
258 val = bus_read_2(reg, BSR);
259 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
270 val = bus_read_2(reg, BAR);
271 val = BAR_ADDRESS(val);
272 if (rman_get_start(reg) != val) {
275 "I/O resource address %lx\n", val,
284 val = bus_read_2(reg, REV);
285 val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
286 if (smc_chip_ids[val] == NULL) {
288 device_printf(dev, "Unknown chip revision: %d\n", val);
293 device_set_desc(dev, smc_chip_ids[val]);
304 uint16_t val;
349 val = smc_read_2(sc, REV);
350 sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
351 sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT;
938 uint32_t val;
948 val = smc_read_2(sc, MGMT);
952 return (val);
956 smc_mii_bitbang_write(device_t dev, uint32_t val)
968 smc_write_2(sc, MGMT, val);
977 int val;
985 val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg);
988 return (val);