dev/siba/siba_core.c

178 	struct siba_cc *scc;
194 	scc = &siba->siba_cc;
195 	if (scc->scc_dev != NULL) {
196 		siba_cc_pmu_init(scc);
197 		siba_cc_power_init(scc);
198 		siba_cc_clock(scc, SIBA_CLOCK_FAST);
199 		siba_cc_powerup_delay(scc);
760 siba_cc_clock(struct siba_cc *scc, enum siba_clock clock)
762 	struct siba_dev_softc *sd = scc->scc_dev;
774 	    (scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0)
779 		tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) &
784 		SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, tmp);
789 		SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW,
790 		    SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) |
796 		SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW,
797 		    (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) |
907 siba_cc_pmu_init(struct siba_cc *scc)
911 	struct siba_dev_softc *sd = scc->scc_dev;
916 	if ((scc->scc_caps & SIBA_CC_CAPS_PMU) == 0)
919 	pmucap = SIBA_CC_READ32(scc, SIBA_CC_PMUCAPS);
920 	scc->scc_pmu.rev = (pmucap & SIBA_CC_PMUCAPS_REV);
923 	    scc->scc_pmu.rev, pmucap);
925 	if (scc->scc_pmu.rev >= 1) {
927 			SIBA_CC_MASK32(scc, SIBA_CC_PMUCTL,
930 			SIBA_CC_SET32(scc, SIBA_CC_PMUCTL,
937 		siba_cc_pmu1_pll0_init(scc, 0 /* use default */);
941 		siba_cc_pmu1_pll0_init(scc, 0 /* use default */);
950 		if (SIBA_CC_READ32(scc, SIBA_CC_CHIPSTAT) &
956 		siba_cc_pmu0_pll0_init(scc, 0 /* use default */);
970 		siba_cc_pmu0_pll0_init(scc, 0 /* use default */);
982 			SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL,
984 			SIBA_CC_WRITE32(scc, SIBA_CC_PMU_UPDNTM,
990 			SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL,
994 				SIBA_CC_WRITE32(scc, SIBA_CC_PMU_DEPMSK,
998 				SIBA_CC_SET32(scc, SIBA_CC_PMU_DEPMSK,
1002 				SIBA_CC_MASK32(scc, SIBA_CC_PMU_DEPMSK,
1014 		SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MINRES, min);
1016 		SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MAXRES, max);
1020 siba_cc_power_init(struct siba_cc *scc)
1022 	struct siba_softc *siba = scc->scc_dev->sd_bus;
1027 			SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0x3a4);
1029 			SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0xa4);
1032 	if ((scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0)
1035 	if (scc->scc_dev->sd_id.sd_rev >= 10)
1036 		SIBA_CC_WRITE32(scc, SIBA_CC_CLKSYSCTL,
1037 		    (SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) &
1040 		maxfreq = siba_cc_clockfreq(scc, 1);
1041 		SIBA_CC_WRITE32(scc, SIBA_CC_PLLONDELAY,
1043 		SIBA_CC_WRITE32(scc, SIBA_CC_FREFSELDELAY,
1049 siba_cc_powerup_delay(struct siba_cc *scc)
1051 	struct siba_softc *siba = scc->scc_dev->sd_bus;
1055 	    !(scc->scc_caps & SIBA_CC_CAPS_PWCTL))
1058 	min = siba_cc_clockfreq(scc, 0);
1059 	scc->scc_powerup_delay =
1060 	    (((SIBA_CC_READ32(scc, SIBA_CC_PLLONDELAY) + 2) * 1000000) +
1065 siba_cc_clockfreq(struct siba_cc *scc, int max)
1070 	src = siba_cc_clksrc(scc);
1071 	if (scc->scc_dev->sd_id.sd_rev < 6) {
1076 	} else if (scc->scc_dev->sd_id.sd_rev < 10) {
1080 			div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) >> 16) +
1087 		div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) >> 16) + 1) * 4;
1105 siba_cc_pmu1_pll0_init(struct siba_cc *scc, uint32_t freq)
1107 	struct siba_dev_softc *sd = scc->scc_dev;
1115 		scc->scc_pmu.freq = 20000;
1121 	scc->scc_pmu.freq = e->freq;
1123 	pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1134 		SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
1137 		SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
1146 		if (!(SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) &
1151 	if (SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) & SIBA_CC_CLKCTLSTATUS_HT)
1154 	pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL0);
1158 	siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, pll);
1160 	pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL2);
1164 	siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, pll);
1166 	pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL3);
1169 	siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, pll);
1172 		pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL5);
1175 		siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, pll);
1178 	pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1183 	SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu);
1187 siba_cc_pmu0_pll0_init(struct siba_cc *scc, uint32_t xtalfreq)
1189 	struct siba_dev_softc *sd = scc->scc_dev;
1204 	scc->scc_pmu.freq = e->freq;
1206 	pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1218 		SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
1220 		SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
1224 		SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES,
1226 		SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES,
1231 		tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS);
1236 	tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS);
1241 	pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL0);
1246 	siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL0, pll);
1249 	pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL1);
1256 	siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL1, pll);
1259 	pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL2);
1262 	siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL2, pll);
1265 	pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
1270 	SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu);
1274 siba_cc_clksrc(struct siba_cc *scc)
1276 	struct siba_dev_softc *sd = scc->scc_dev;
1291 		switch (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) & 0x7) {
1322 siba_cc_pll_read(struct siba_cc *scc, uint32_t offset)
1325 	SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset);
1326 	return (SIBA_CC_READ32(scc, SIBA_CC_PLLCTL_DATA));
1330 siba_cc_pll_write(struct siba_cc *scc, uint32_t offset, uint32_t value)
1333 	SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset);
1334 	SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_DATA, value);
1725 	struct siba_cc *scc;
1730 	scc = &siba->siba_cc;
1731 	if (!scc->scc_dev || scc->scc_dev->sd_id.sd_rev < 5)
1733 	siba_cc_clock(scc, SIBA_CLOCK_SLOW);
2044 siba_cc_suspend(struct siba_cc *scc)
2047 	siba_cc_clock(scc, SIBA_CLOCK_SLOW);
2051 siba_cc_resume(struct siba_cc *scc)
2054 	siba_cc_power_init(scc);
2055 	siba_cc_clock(scc, SIBA_CLOCK_FAST);
2100 	struct siba_cc *scc = &siba->siba_cc;
2113 		siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]),
2136 		siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]),
2146 	struct siba_cc *scc = &siba->siba_cc;
2156 		SIBA_CC_SET32(scc, SIBA_CC_PMU_MINRES, 1 << ldo);
2158 		SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, ~(1 << ldo));
2159 	SIBA_CC_READ32(scc, SIBA_CC_PMU_MINRES);