nxge/xgehal/xgehal-ring.c

392 	u64 val64;
413 	val64 = __hal_ring_item_dma_addr(ring->mempool,
416 	        val64, &bar0->prc_rxd0_n[ring->channel.post_qid]);
419 	        ring->channel.post_qid, (unsigned long long)val64);
421 	val64 = xge_os_pio_mem_read64(ring->channel.pdev,
425 	    val64 |= XGE_HAL_PRC_CTRL_RTH_DISABLE;
427 	val64 |= XGE_HAL_PRC_CTRL_RC_ENABLED;
429 	val64 |= vBIT((queue->buffer_mode >> 1),14,2);/* 1,3 or 5 => 0,1 or 2 */
430 	val64 &= ~XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
431 	val64 |= XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(
435 	val64 |= XGE_HAL_PRC_CTRL_NO_SNOOP(queue->no_snoop_bits);
439 	        val64 |= XGE_HAL_PRC_CTRL_GROUP_READS;
443 	        val64 |= XGE_HAL_PRC_CTRL_BIMODAL_INTERRUPT;
446 	        val64, &bar0->prc_ctrl_n[ring->channel.post_qid]);
449 	val64 = xge_os_pio_mem_read64(ring->channel.pdev,
451 	val64 |= XGE_HAL_RX_PA_CFG_SCATTER_MODE(ring->config->scatter_mode);
452 	val64 |= (XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI | XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL);
454 	val64 &= ~XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(1);
455 	val64 |= XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(ring->config->strip_vlan_tag);
458 	        val64, &bar0->rx_pa_cfg);
469 	u64 val64;
476 	val64 = xge_os_pio_mem_read64(ring->channel.pdev,
479 	val64 &= ~((u64) XGE_HAL_PRC_CTRL_RC_ENABLED);
481 	        val64, &bar0->prc_ctrl_n[ring->channel.post_qid]);
489 	u64 val64;
494 	val64 = 0;
498 	    val64 |= vBIT(hldev->config.ring.queue[i].priority,
501 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
504 	        (unsigned long long)val64);
507 	val64 = 0;
511 	    val64 |= vBIT(hldev->config.ring.queue[i].dram_size_mb,(i*8),8);
513 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
516 	        (unsigned long long)val64);
526 	    val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
535 	                val64 |= (BIT(i) >> (j*8));
538 	    xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
541 	               (unsigned long long)val64);
559 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
561 	val64 |= 0x0000000000010000;
562 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
565 	val64 |= 0x003a000000000000;
566 	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
572 	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
574 	val64 |= XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE |
576 	__hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, (u32)(val64>>32),
579 	__hal_pio_mem_write32_lower(hldev->pdev, hldev->regh0, (u32)val64,
587 	    val64 = XGE_HAL_MC_RLDRAM_SET_REF_PERIOD(0x0279);
588 	    xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,
591 	    val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
594 	               (unsigned long long)val64);
596 	    val64 = 0x0003570003010300ULL;
597 	    xge_os_pio_mem_write64(hldev->pdev, hldev->regh0, val64,