Lines Matching defs:BIT_6
184 #define BIT_6 (1 << 6)
302 #define PCI_EXT_PATCH_2 BIT_6
366 #define PCI_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */
796 #define CS_CL_SW_IRQ BIT_6 /* Clear IRQ SW Request */
809 #define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */
839 #define Y2_IS_PTP_TIST BIT_6 /* PTP TIme Stamp (Yukon Optima) */
933 #define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */
987 #define TST_FRC_DPERR_MW BIT_6 /* force DATAPERR on MST WR */
1072 #define TXA_DIS_FSYNC BIT_6 /* Disable force of sync Tx queue */
1108 #define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */
1166 #define RB_WP_T_ON BIT_6 /* Write Pointer Test On */
1230 #define WOL_CTL_DIS_PME_ON_PATTERN BIT_6
1351 #define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */
1358 #define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */
1416 #define PHY_M_PC_SH_TP_SEL BIT_6 /* Shielded Twisted Pair Select */
1429 #define PHY_M_PS_MDI_X_STAT BIT_6 /* MDI Crossover Stat (1=MDIX) */
1454 #define PHY_M_IS_MDI_CHANGE BIT_6 /* MDI Crossover Changed */
1503 #define PHY_M_LEDC_TX_C_LSB BIT_6 /* Tx Control (LSB, 88E1111 only) */
1548 #define PHY_M_EC2_FI_IMPED BIT_6 /* Fiber Input Impedance */
1832 #define GM_GPCR_FL_PASS BIT_6 /* Force Link Pass */
1915 #define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */
1973 #define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */
1992 #define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */
2071 #define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */